SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading

Yu, Wancong; Huang, Rongjin; Xu, Sarah Q.; Wang, Sung-En; Kan, Edwin C.; Suh, G. Edward

doi:10.1145/2000064.2000094

Cited by 51 publications

(17 citation statements)

References 12 publications

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“…The read/write times to CMOS-and TFET-based registers and the total execution time are collected from the modified GPGPU-Sim to evaluate both RF dynamic and leakage energy consumption. Our energy estimation is consistent with previous studies [3,4,8].…”

Section: Evaluations 41 Experimental Methodologysupporting

confidence: 93%

“…The authors further extended their work to the compiler level and explored register allocation algorithms to improve register energy efficiency [5]. Yu et al integrated embedded DRAM and SRAM cells to reduce area and energy [3]. In addition, several works have been done on GPGPU register leakage power optimization.…”

Section: Related Workmentioning

confidence: 99%

“…For example, Nvidia Fermi GPU supports more than 20,000 parallel threads and contains 2MB register files [7]. Accessing such sizeable register files leads to massive power consumption [2][3][4][5][6]. It has been reported that the register files consume 15%-20% of the GPU stream multiprocessor's power [8].…”

Section: Introductionmentioning

confidence: 99%

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Hybrid CMOS-TFET based register files for energy-efficient GPGPUs

Tan

2013

International Symposium on Quality Electronic Design (ISQED)

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State-of-the-art General-Purpose computing on Graphics Processing Unit (GPGPU) is facing severe power challenge due to the increasing number of cores placed on a chip with decreasing feature size. In order to hide the long latency operations, GPGPU employs the fine-grained multithreading among numerous active threads, leading to the sizeable register files with massive power consumption. Exploring the optimal power savings in register files becomes the critical and first step towards the energyefficient GPGPUs. The conventional method to reduce dynamic power consumption is the supply voltage scaling, and the inter-bank tunneling FETs (TFETs) are the promising candidates compared to CMOS for low voltage operations regarding to both leakage and performance. However, always executing at the low voltage (so that low frequency) will result in significant performance degradation. In this study, we propose the hybrid CMOS-TFET based register files. To optimize the register power consumption, we allocate TFET-based registers to threads whose execution progress can be delayed to some degree to avoid the memory contentions with other threads, and the CMOS-based registers are still used for threads requiring normal execution speed. Our experimental results show that the proposed technique achieves 30% energy (including both dynamic and leakage) reduction in register files with little performance degradation compared to the baseline case equipped with naive power optimization technique.

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Section: Evaluations 41 Experimental Methodologysupporting

confidence: 93%

Section: Related Workmentioning

confidence: 99%

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Hybrid CMOS-TFET based register files for energy-efficient GPGPUs

Tan

2013

International Symposium on Quality Electronic Design (ISQED)

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“…Prior work has explored improving register file's efficiency by reducing the number of entries [2,27], reducing the number of ports [18], and reducing the number of accesses [20,25]. These approaches have been explored for traditional CPUs, VLIW processors [28,29,30], and streaming processors [8,22].…”

Section: Related Workmentioning

confidence: 99%

“…Swensen and Patt show that a two-level register file hierarchy can provide nearly all of the performance benefit of a large register file on scientific codes [24]. Recent work, proposes using a hybrid SRAM / embedded DRAM (eDRAM) register file to reduce the register file access energy of a GPU [27]. They propose changes to the thread scheduler to minimize the effect of fetching values from eDRAM.…”

Section: Related Workmentioning

confidence: 99%

A compile-time managed multi-level register file hierarchy

Gebhart

Keckler

Dally

2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

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As processors increasingly become power limited, performance improvements will be achieved by rearchitecting systems with energy efficiency as the primary design constraint. While some of these optimizations will be hardware based, combined hardware and software techniques likely will be the most productive. This work redesigns the register file system of a modern throughput processor with a combined hardware and software solution that reduces register file energy without harming system performance. Throughput processors utilize a large number of threads to tolerate latency, requiring a large, energy-intensive register file to store thread context. Our results show that a compiler controlled register file hierarchy can reduce register file energy by up to 54%, compared to a hardware only caching approach that reduces register file energy by 34%. We explore register allocation algorithms that are specifically targeted to improve energy efficiency by sharing temporary register file resources across concurrently running threads and conduct a detailed limit study on the further potential to optimize operand delivery for throughput processors. Our efficiency gains represent a direct performance gain for power limited systems, such as GPUs.

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