SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading

Yu, Wancong; Huang, Rongjin; Xu, Sarah Q.; Wang, Sung-En; Kan, Edwin C.; Suh, G. Edward

doi:10.1145/2024723.2000094

Cited by 16 publications

(22 citation statements)

References 12 publications

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“…RFC replaces accesses to a large and power hungry register file with accesses to a small and power-efficient cache. Yu et al [1] proposed hybrid memory which integrates SRAM and DRAM cells to reduce area and power of register file in GPGPUs. Each SRAM cell is augmented with N DRAM cells.…”

Section: Related Workmentioning

confidence: 99%

Reducing shift penalty in Domain Wall Memory through register locality

Atoofian¹

2015

2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)

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General-purpose graphics processing units (GPGPUs) have the ability to execute hundreds to thousands of threads simultaneously. Extreme multithreading requires a large register file to hold state of executing threads and facilitate context switching. As feature size reduces, power consumption in the large register file becomes a major concern.In this work, we exploit Domain Wall Memory (DWM) which is a spin-based memory to reduce power consumption in register file. DWM is a promising technology and offers non-volatility, high energy efficiency, and high density by storing several bits into the domains of a ferromagnetic wire. However, despite of favourable properties of DMW over SRAM technology, DWM poses a unique challenge that the bits must be accessed serially through shift operations, leading to variable and potentially higher access latencies. To address this challenge, we propose a new predictive shift policy. In this policy, we exploit register locality across threads and predict source and destination operands of instructions. We record history of registers accessed by instructions and shift magnetic domains of DWM tracks for subsequent instructions, speculatively. Over a wide range of applications from NVIDIA CUDA SDK, ISPASS, and Rodinia, our predictive scheme achieves dramatic energy saving over an SRAM register file while changing performance negligibly.

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Section: Related Workmentioning

confidence: 99%

Reducing shift penalty in Domain Wall Memory through register locality

Atoofian¹

2015

2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)

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“…In essence, we utilize the cross coupled inverters of each SRAM cell also as the sense amplifiers for the cached bits to achieve efficiency in area. Another implementation of the multibit SRAM is a SRAM/DRAM hybrid, a volatile variation [3] of the multibit SRAM.…”

Section: Multibit Hybrid Sram Cellsmentioning

confidence: 99%

Nonvolatile multibit SRAM, bit level caching, and multi-context computing for IoT

2015

2015 15th Non-Volatile Memory Technology Symposium (NVMTS)

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We propose a new memory hierarchy for energy conscious internet of things (IoT) integrated circuits. In this scheme a new type of SRAM cell -hybrid of SRAM/DRAM or SRAM/NVM memory -that is capable of storing multiple bits are used to bring caching to the bit level, near processor cores. This new scheme is expected to have energy efficiency advantage over traditional memory hierarchy for multi-context computation, especially suitable for many IoT applications.

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“…Several works [3,13,32] proposed to save register file power. Leng [18] saves dynamic power of the execution units and register file by clock gating and DVFS.…”

Section: Related Workmentioning

confidence: 99%

Pats

Annavaram

2014

Proceedings of the 23rd International Conference on Parallel Architectures and Compilation

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General purpose computing using graphics processing units (GPGPUs) is an attractive option to achieve power efficient throughput computing. But the power efficiency of GPGPUs can be significantly curtailed in the presence of divergence. This paper evaluates two important facets of this problem. First, we study the branch divergence behavior of various GPGPU workloads. We show that only a few branch divergence patterns are dominant in most workloads. In fact only five branch divergence patterns account for 60% of all the divergent instructions in our workloads. In the second part of this work we exploit this branch divergence pattern bias to propose a new divergence pattern aware warp scheduler, called PATS. PATS prioritizes scheduling warps with the same divergence pattern so as to create long idleness windows for any given execution lane. The long idleness windows are then exploited for efficiently power gating the unused lanes while amortizing the gating overhead. We describe the architectural implementation details of PATS and evaluate the power and performance impact of PATS. Our proposed design significantly improves power gating efficiency of GPGPUs with minimal performance overhead.

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SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading

Cited by 16 publications

References 12 publications

Reducing shift penalty in Domain Wall Memory through register locality

Reducing shift penalty in Domain Wall Memory through register locality

Nonvolatile multibit SRAM, bit level caching, and multi-context computing for IoT

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