SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS

Frustaci, Fabio; Khayatzadeh, Mahmood; Blaauw, David; Sylvester, Dennis; Alioto, Massimo

doi:10.1109/jssc.2015.2408332

Cited by 61 publications

(30 citation statements)

References 18 publications

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“…The effects of these techniques at bit level can vary depending on DRAM architectures and will be discussed in Section III-A. As regards SRAMs, the techniques are more varied and applied at circuit level [7], [8], [18]. In general, energy reduction is obtained by scaling supply voltage, but the effects at bit level can be different, depending on circuit design.…”

Section: Memoriesmentioning

confidence: 99%

“…Their presence is the result, in general, of design implementations introduced to significantly reduce energy consumption [4], [5], [6]. Different strategies can be actively used in order to reduce energy consumption introducing approximation: in SRAM, for example, supply voltage scaling can be applied [7], [8]; while in DRAM refresh rate can be reduced or completely disabled [9], [10], [4], since the refresh operation degrades performance and wastes energy (e.g. when the system is in standby mode, it can reach up to 50% of total power consumption [1]).…”

Section: Introductionmentioning

confidence: 99%

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AppropinQuo: A Platform Emulator for Exploring the Approximate Memory Design Space

Stazi

Mastrandrea

Olivieri

et al. 2018

2018 New Generation of CAS (NGCAS)

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In this work we present AppropinQuo, a flexible and configurable emulator for embedded platforms with approximate memory. The emulator includes models of the effects of approximate memory circuits and architectures, that depend on the internal structure and organization of the cells. The ability to emulate a complete platform, including CPU, peripherals and hardware-software interactions, is particularly important since it allows to execute the application as on the real board, reproducing the effects of errors on output. In fact, output quality is related not only to error rate but it also depends on the application, implementation and its data representation.AppropinQuo allows to run actual applications and operating system as on the physical platform, to analyze the behavior and to expose the effects of specific approximate memory circuits and architectures on output quality. By exploring the design space regarding approximate memories, a complete characterization of the application is possible, as a step toward the determination of the trade-off between saved energy and output quality (energyquality tradeoff).

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Section: Memoriesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

AppropinQuo: A Platform Emulator for Exploring the Approximate Memory Design Space

Stazi

Mastrandrea

Olivieri

et al. 2018

2018 New Generation of CAS (NGCAS)

View full text Add to dashboard Cite

show abstract

“…As shown in Fig. 1, considerable savings can be achieved by using nonvolatile memory (NVM) to store program data in power-off mode [1]- [17] in conjunction with volatile memory, such as SRAM or DRAM [18]- [22], for computing in power-on mode. NAND-flash [23]- [25] is commonly used for off-chip storage and embedded Flash (eFlash) [26]- [28] can be found in on-chip NVM.…”

Section: Introductionmentioning

confidence: 99%

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices

Chang

Lee

Chen

et al. 2015

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Memristive devices have shown considerable promise for on-chip nonvolatile memory and computing circuits in energyefficient systems. However, this technology is limited with regard to speed, power, VDDmin, and yield due to process variation in transistors and memrisitive devices as well as the issue of read disturbance. This paper examines trends in the design of device and circuits for on-chip nonvolatile memory using memristive devices as well as the challenges faced by researchers in its further development. Several silicon-verified examples of circuitry are reviewed in this paper, including those aimed at high-speed, area-efficient, and low-voltage applications.Index Terms-Memristive device, memristor, nonvolatile memory, recent developments in resistive memory (ReRAM), resistive RAM.

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“…b) illustrates a reverse water-filling interpretation of(17). For a bit position b such that1 ν < 4 b √ 2πσ , by modifying…”

mentioning

confidence: 99%

Generalized Water-filling for Source-aware Energy-efficient SRAMs

Kim

Kang

Varshney

et al. 2018

IEEE Trans. Commun.

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Conventional low-power static random access memories (SRAMs) reduce read energy by decreasing the bit-line voltage swings uniformly across the bit-line columns. This is because the read energy is proportional to the bit-line swings. On the other hand, bit-line swings are limited by the need to avoid decision errors especially in the most significant bits. We propose a principled approach to determine optimal non-uniform bit-line swings by formulating convex optimization problems. For a given constraint on mean squared error of retrieved words, we consider criteria to minimize energy (for low-power SRAMs), maximize speed (for high-speed SRAMs), and minimize energy-delay product.These optimization problems can be interpreted as classical water-filling, ground-flattening and waterfilling, and sand-pouring and water-filling, respectively. By leveraging these interpretations, we also propose greedy algorithms to obtain optimized discrete swings. Numerical results show that energyoptimal swing assignment reduces energy consumption by half at a peak signal-to-noise ratio of 30dB for an 8-bit accessed word. The energy savings increase to four times for a 16-bit accessed word. I. INTRODUCTIONVon Neumann computing architectures separate memory units from computing units so there is frequent data access that consumes enormous energy. Since static random access memories (SRAMs) access requires more energy than arithmetic operations [1], SRAM access energy accounts for the significant part of the total energy consumption in many information processing This work was supported in part by Systems on Nanoscale Information fabriCs (SONIC), one of the six SRC STARnet Centers, sponsored by MARCO and DARPA. arXiv:1710.07153v3 [cs.IT] 29 Nov 2017 formulate convex optimization problems whose objectives are as follows: C1. Minimize energy (low-power SRAMs), C2. Maximize speed (high-speed SRAMs), C3. Minimize energy-delay product (EDP).Solutions to these convex problems yield optimal performance that is theoretically attainable.By casting read access for SRAMs as communication over parallel channels, we investigate the fundamental trade-offs between physical resources (energy, delay, and EDP) and a fidelity (MSE) constraint.In addition, we provide generalized water-filling interpretations for our optimal solutions. This follows since accessing a B-bit word is equivalent to communicating information through B parallel channels. In classical water-filling, the ground represents the noise levels of parallel channels [20], [21]. On the other hand, the importance of each bit position determines the ground level in our optimization problems. Each optimization problem has its own interpretation depending on its objective function: water-filling (C1), ground-flattening and water-filling (C2), and sand-pouring and water-filling (C3), respectively. We also observe interesting connections between our problems and variants on water-filling such as constant-power water-filling [22],[23] and mercury/water-filling [24]. Also, we show that the proposed ...

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SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS

Cited by 61 publications

References 18 publications

AppropinQuo: A Platform Emulator for Exploring the Approximate Memory Design Space

AppropinQuo: A Platform Emulator for Exploring the Approximate Memory Design Space

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices

Generalized Water-filling for Source-aware Energy-efficient SRAMs

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