SRAM FPGA Reliability Analysis for Harsh Radiation Environments

Ostler, Patrick; Caffrey, Michael; Gibelyou, Derrick; Graham, Paul; Morgan, Keith S.; Pratt, B.; Quinn, Heather; Wirthlin, Michael

doi:10.1109/tns.2009.2033381

Cited by 113 publications

(67 citation statements)

References 11 publications

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“…Among other things, the authors investigate how multiple TMR partitions increase the reliability. Ostler et al present a reliability analysis of SRAM-based FPGAs in [7]. The methodology takes particular radiation environments into account and is based on fault injection experiments.…”

Section: Availability Analysis Methodologymentioning

confidence: 99%

Availability analysis for satellite data processing systems based on SRAM FPGAs

Siegle

Vladimirova

Ilstad

et al. 2016

IEEE Trans. Aerosp. Electron. Syst.

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Abstract-This paper presents a novel methodology, which allows a systematic availability analysis of satellite payload data processing systems implemented on SRAM-based FPGAs. The methodology allows (i) comparison of different Fault Detection, Isolation and Recovery (FDIR) schemes and (ii) prediction of the expected system availability in a particular radiation environment. Furthermore, it advances the state of the art by analysing embedded Block RAMs and employing a novel fault injection algorithm that enables more complex stochastic models. The applicability of the method is demonstrated by a case study representing a high availability payload data processing application. Since Block RAMs are also taken into account, the availability prediction precision is greatly increased. It is shown that the reliability prediction for two border cases, in which the Block RAMs are either ignored or assumed to be fully susceptible, can differ as much as 75%. With the proposed Block RAM profiling tool it is possible to determine a realistic reliability figure that is eventually required for the accurate estimation of the system availability.

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Section: Availability Analysis Methodologymentioning

confidence: 99%

Availability analysis for satellite data processing systems based on SRAM FPGAs

Siegle

Vladimirova

Ilstad

et al. 2016

IEEE Trans. Aerosp. Electron. Syst.

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“…Once the task unreliability Q τi is known, the failure rate (number of failures per time unit per task) of a task during its execution can be estimated as follows [2]:…”

Section: Reliability and Fault Modelmentioning

confidence: 99%

Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms

Ramezani

Sedaghat

Naghibzadeh

et al. 2017

IEEE Trans. Aerosp. Electron. Syst.

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Abstract-This paper addresses the problem of reliability and makespan optimization of hardware task graphs in reconfigurable platforms by applying fault tolerance (FT) techniques to the running tasks based on the exploration of the Pareto set of solutions. In the presented solution, in contrast to existing approaches in the literature, task graph scheduling, tasks parallelism, reconfiguration delay, and FT requirements are taken into account altogether. This paper firstly presents a model for hardware task graphs, task prefetch and scheduling, reconfigurable computer and a fault model for reliability. Then, a mathematical model of an integer nonlinear multi-objective optimization problem is presented for improving the FT of hardware task graphs, scheduled in partially reconfigurable platforms. Experimental results show the positive impacts of choosing the FT techniques selected by the proposed solution, which is named Pareto-based. Thus, in comparison to non-fault-tolerant designs or other stateof-the-art FT approaches, without increasing makespan, about 850% Mean Time To Failure (MTTF) improvement is achieved and, without degrading reliability, makespan is improved by 25%. In addition, experiments in fault-varying environments have demonstrated that the presented approach outperforms existing state-of-the-art adaptive FT techniques in terms of both MTTF and makespan.

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“…Complementary SEU tolerance techniques have been incorporated to enable the use of SRAM-based FPGAs in harsh radiation environments: Error Detection And Correction (EDAC, such as TMR and majority voting) at Application Layer, and memory scrubbing at Configuration Layer. The reliability improvement of TMR systems when scrubbing is applied has been deeply analyzed in [4].…”

Section: See Can Be Reversible (Soft Errors) or Destructive (Hard Errmentioning

confidence: 99%

“…If more than one FIE is detected within a scrub cycle, or FIEs are detected in consecutive scrub cycles at any given time, one should consider increasing the scrub rate. A shorter scrub cycle improves the Mean Time To Failure (MTTF) figure [4]. Therefore, the trade-off between reliability and power consumption must be managed.…”

Section: Fig 4 Self-reference Scrubber Fsm Statesmentioning

confidence: 99%

Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs

Herrera-Alzu

López‐Vallejo

2011

Lecture Notes in Computer Science

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Abstract. SRAM-based FPGAs are sensitive to radiation effects. Soft errors can appear and accumulate, potentially defeating mitigation strategies deployed at the Application Layer. Therefore, Configuration Memory scrubbing is required to improve radiation tolerance of such FPGAs in space applications. Virtex FPGAs allow runtime scrubbing by means of dynamic partial reconfiguration. Even with scrubbing, intra-FPGA TMR systems are subjected to common-mode errors affecting more than one design domain. This is solved in inter-FPGA TMR systems at the expense of a higher cost, power and mass. In this context, a self-reference scrubber for device-level TMR system based on Xilinx Virtex FPGAs is presented. This scrubber allows for a fast SEU/MBU detection and correction by peer frame comparison without needing to access a golden configuration memory.

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SRAM FPGA Reliability Analysis for Harsh Radiation Environments

Cited by 113 publications

References 11 publications

Availability analysis for satellite data processing systems based on SRAM FPGAs

Availability analysis for satellite data processing systems based on SRAM FPGAs

Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms

Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs

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