SRAM Memory Layout Design in 180nm Technology

Abstract

This paper presents a full custom memory layout design of 1KB SRAM, followed by physical verification checks, such as DRC and LVS to validate the layouts implemented. The Layout design technique such as device matching, routing matching, half-cell and symmetry has been followed carefully. The layouts were implemented using CADENCE EDA, Virtuoso platform was used for schematic and layout design. Assura physical verification environment was used for validating the layout designs. Technology nodes used are gpdk 180nm and 45nm. The full custom layout of 1KB SRAM architecture was successfully designed.

Development of SRAM-APB protocol interface and verification

“…For networking as well as other high-performance purposes, the QDR SRAM architecture offers the random memory access functionality required. Memory is a critical impediment in many applications for achieving improved system efficiency [9]. Kumar et al [15,22] use Verilog Hardware Description Language (HDL) to develop an APB Bridge incorporating a clock skew minimising approach.…”

“…The DDR assigns a synchronous knowledgeinterconnection as well as many control signals to the DDR SDRAM Memory [26]. This DDR SDRAM practical approach incorporates established deferrals and stage linkages throughout data sources and yields and ensures that tickers and delayed signals are free of bugs [9,27].…”

“…Cypress is the world leader in Synchronous (Sync) SRAM, with lead times of six weeks or less, 99 percent or greater on-time shipment, and legacy product support lasting up to 20 years, having supplied more than 2.7 billion aggregate units. Customers in numerous market categories, including networking, automobiles, consumer electronics, commercial, healthcare, aviation, and defence, choose Cypress as their SRAM supplier [9].…”

Content-Addressable Memory System Using a Nanoelectromechanical Memory Switch

“…A schematic diagram of the CMOS-based BCAM single-bit cell is shown in Figure 4a, and the data encoding is depicted in Figure 4b. The transistor sizing values for the CMOS-based BCAM single-bit cell are summarized in Table 1 [3].…”

“…Conventional random-access memory devices, such as static random-access memory (SRAM) and dynamic random-access memory (DRAM), store data during a write cycle and read a stored memory during a read cycle. As a specific memory location, called the address, must be assigned during this process, sequential memory operations are inevitable for random-access memory devices [1][2][3][4][5].…”