SRAM Radiation Hardening Through Self-Refresh Operation and Error Correction

Siddiqui, M. Sultan M.; Sharma, Ruchi; Le, Van Loi; Yoo, Taegeun; Chang, Ik-Joon; Kim, Tony Tae-Hyoung

doi:10.1109/tdmr.2020.2994769

Cited by 16 publications

(4 citation statements)

References 13 publications

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“…For forward diagonal parity, as shown in Fig. 2, the 1st forward diagonal has only one cell as [0], [0], the 2nd diagonal has a two cells as [0], [1] and [1]…”

Section: Forward and Backward Parity Calculationmentioning

confidence: 99%

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Tolerating Soft Errors with Horizontal-Vertical-Diagonal-N-Queen (HVDNQ) Parity

2021

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A new error detection and correction methodology, defined as Horizontal-Vertical-Diagonal-N-Queen-Parity (HVDNQ), is proposed in this paper. This approach relies on five different types of parities: horizontal parity, vertical parity, forward diagonal parity, backward diagonal parity, and queen parity. This method works on an N X N cell area and can correct multibit upsets. The experimental analysis validates the effectiveness of the proposed methodology by comparing its efficiency with existing methodologies. In different varieties of error patterns such as equilateral triangle, pentagon, hexagon etc., the capability of error detection and correction of HVDNQ is much better than existing methods.

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“…For forward diagonal parity, as shown in Fig. 2, the 1st forward diagonal has only one cell as [0], [0], the 2nd diagonal has a two cells as [0], [1] and [1]…”

Section: Forward and Backward Parity Calculationmentioning

confidence: 99%

“…Systems complexity is increasing day by day with the advancement of modern circuitry. As a result, systems have become more prone to soft errors [1]. Embedded systems, having high complexity, face casualty in this matter.…”

Section: Introductionmentioning

confidence: 99%

Tolerating Soft Errors with Horizontal-Vertical-Diagonal-N-Queen (HVDNQ) Parity

2021

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“…However, soft errors are induced in the near-threshold operation region due to the effects of alpha particles [15]. High-energy alpha particles interact with the memory cell and interrupt operations or even cause damage [16]. SRAM designs can be categorized based on interconnections with the inverter as i) cross-coupled standard inverter, ii) cross-coupled Schmitt-trigger (ST) inverter, and iii) cross-coupled ST inverter with a standard inverter.…”

Section: Introductionmentioning

confidence: 99%

Design of Low Power Transmission Gate Based 9T SRAM Cell

Rooban¹,

Leela²,

Rahman³

et al. 2022

Computers, Materials &Amp; Continua

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Considerable research has considered the design of low-power and high-speed devices. Designing integrated circuits with low-power consumption is an important issue due to the rapid growth of high-speed devices. Embedded static random-access memory (SRAM) units are necessary components in fast mobile computing. Traditional SRAM cells are more energyconsuming and with lower performances. The major constraints in SRAM cells are their reliability and low power. The objectives of the proposed method are to provide a high read stability, low energy consumption, and better writing abilities. A transmission gate-based multi-threshold single-ended Schmitt trigger (ST) 9T SRAM cell in a bit-interleaving structure without a write-back scheme is proposed. Herein, an ST inverter with a single bit-line design is used to attain the high read stability. A negative assist technique is applied to alter the trip voltage of the single-ended ST inverter. The multithreshold complementary metal oxide semiconductor (MTCMOS) technique is adopted to reduce the leakage power in the proposed single-ended TG-ST 9T SRAM cell. The proposed system uses a combination of standard and ST inverters, which results in a large read stability. Compared with the previous ST 9T, ST 11T, 11T, 10T, and 7T SRAM cells, the proposed cell is implemented in Cadence Virtuoso ADE with 45-nm CMOS technology and consumes 35.80%, 42.09%, 31.60%, 12.54%, and 31.60% less energy for read operations and 73.59%, 93.95%, 92.76%, 89.23%, and 85.78% less energy for write operations, respectively.

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“…In IC's, a charge-sharing effect between NMOS transistors within the circuit occurs, making the heavy-ion strike's distortion more severe. As a result, by adopting multi NMOS transistor designs to lessen the charge-sharing effect inside the circuit, the circuit's SEU dependability can be boosted even further [10][11][12]. Using more NMOS transistors and a lower transistor size will have great radiation-hardened capabilities and good write ability [14].…”

Section: Introductionmentioning

confidence: 99%

Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

Gavaskar¹,

Sivaranjani²,

Elango³

et al. 2022

Wireless Pers Commun

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One of the most critical functions of a computer is memory, as it would be impossible for it to function e ciently without it. The main memory of a computer is known as Random Access Memory (RAM). It stores operating system software, applications, and other data for the central processor unit (CPU) to perform operations swiftly and e ciently. Unfortunately, traditional static RAM (SRAMs) in aerospace applications suffers from high soft error issues such as Single Event Upset (SEU). To overcome the soft error problems, many Radiation-Hardened-Based Designs (RHBD) and Radiation-Hardened-Polar Designs (RHPD) have been developed, such as 12T We-Quatro, twelve-transistor (12T) Dice SRAM cells, and so on. However, they consume more total and static power, as well as have more delay and area. In this article, an RHPD and RHBD 12T SRAM cell is proposed to reduce power dissipation and area overhead. Compared to RHPD, the RHBD 12T SRAM cell devours less total and static power, and RHPD cells have less delay. The proposed SRAM cell is implemented in the 32 x 32 array architecture. The power consumption of a 32 x 32 SRAM array with a 12T RHBD SRAM cell is 1.33mW, which is 10.1% less than a 32 x 32 SRAM array with a 12T RHPD SRAM array is 4.23mW. Cadence virtuoso 6.1.5 at 45 nm Generic Process Design Kit (GPDK) technology le is used to simulate the comparative analysis for the SRAM cell.

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SRAM Radiation Hardening Through Self-Refresh Operation and Error Correction

Cited by 16 publications

References 13 publications

Tolerating Soft Errors with Horizontal-Vertical-Diagonal-N-Queen (HVDNQ) Parity

Tolerating Soft Errors with Horizontal-Vertical-Diagonal-N-Queen (HVDNQ) Parity

Design of Low Power Transmission Gate Based 9T SRAM Cell

Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

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