SSTL I/O Standard based environment friendly energyl efficient ROM design on FPGA

Abstract

Abstract-in this work, we are making energy efficient 32-bit ALU by using different classes of LVCMOS IO standard. Here, we are operating our design with operating speed of 4 th generation i7 processor in order to test the compatibility of our design with the latest state of the art technology based processor. When there is no demand of peak performance, then we can save 75.2% Clock power, 75% Logic power, 75.36% Signal power, 81.82% I/O power by operating our device with 1GHz frequency in place of maximum 4GHz. LVCMOS25 having 69.65%, 53.48%, 38.77% more power consumption with respect to LVCMOS12, LVCMOS15, LVCMOS 18 at 2.9GHz respectively. In this we used, VERILOG hardware description language, XILINX ISE simulator, and Virtex-6 FPGA and XPower analyzer.

Power Efficient Frequency Scaled and Thermal-Aware Control Unit Design on FPGA

“…In [8] researchers used Virtex-6 FPGA to design four-bit unsigned up counter by enabling clock and with an asynchronous clear. In [9] authors interfaced Random Access Memory (ROM) design on Virtex-6 FPGA.…”

HSTL and HSUL I/O Standard Based Energy-Efficient Control Unit Circuit Design on FPGA

“…Authors used various SSTL I/O standard to calculate the power of device [10]. An energy-efficient Read-Only Memory (ROM) is designed by authors using various SSTL I/O standard techniques [11]. Power efficient and thermal aware adder circuit is designed on 65 nm FPGA using different HSTL I/O standard [12].…”

Frequency Scaling Based Power Efficient Current Source Design on FPGA

“…In this work authors worked on IO standards of FPGA to study the power consumption of Random Access Memory (RAM). By using Virtex-6 FPGA, authors interfaced RAM to minimize its power consumption [14]. For real-time simulation photovoltaic modules are designed by the authors with the help of FPGA [15].…”