Abstract-in this work, we are making energy efficient 32-bit ALU by using different classes of LVCMOS IO standard. Here, we are operating our design with operating speed of 4 th generation i7 processor in order to test the compatibility of our design with the latest state of the art technology based processor. When there is no demand of peak performance, then we can save 75.2% Clock power, 75% Logic power, 75.36% Signal power, 81.82% I/O power by operating our device with 1GHz frequency in place of maximum 4GHz. LVCMOS25 having 69.65%, 53.48%, 38.77% more power consumption with respect to LVCMOS12, LVCMOS15, LVCMOS 18 at 2.9GHz respectively. In this we used, VERILOG hardware description language, XILINX ISE simulator, and Virtex-6 FPGA and XPower analyzer.

An ideal capacitor will not dissipate any power, but a real capacitor will have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM with frequencies (2.9GHz, 3.3GHz, 3.6GHz, 3.8GHz and 4.0GHz) supported by i7 processor.By using different capacitance there comes is reduction in I/O Power and Total power but not in other Powers like Clock, and Leakage (almost negligible). When capacitance goes from 30pF to 5pF, there is a saving of 28.12% occur in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog.

—Thermal aware design is currently gaining importance in VLSI research domain. In this work, we are going to design thermal aware energy efficient ROM on Virtex-5 FPGA. Ambient Temperature, airflow, and heat sink profile play a significant role in thermal aware hardware design life cycle. Ambient temperature is a temperature of surroundings. Airflow is measured in Linear Feet per Minute (LFM). Medium profile and high profile are two different heat sink profile available in XPower analyzer.When frequency goes from 4.0GHz to 1.0GHz, there is 21.8% reduction in clock power, 75% reduction in I/O Power, 35.6% reduction in leakage power and 53.8% reduction in total power at the same frequency.

In this work, we are using LVDCI I/O standard in energy efficient ROM design on FPGA. There is a 92% reduction in clock power, 50% reduction in signal power, 32-46% reduction in IO's power, and 25-27% reduction in total power, when we scale down frequency from 4.0GHz to 1.0GHz. There is no reduction in clock power and signal power, when we change I/O standard from LVDCI_25 to LVDCI_15, but there is reduction of 61-69% of IO's power and reduction of 16-18% in total power. This design is implemented on Virtex-5 FPGA using Verilog hardware description language and Xilinx ISE simulator. LVDCI_15, LVDCI_18, LVDCI_25, HSLVDCI_15 and HSLVDCI_18 are five different IO standard is in use to design energy efficient ROM. LV stands for Low Voltage, HS means High Speed and DCI means Digitally Control impedance.