Stability analysis of 7T-SRAM cell

Surekha, G.; Balaji, N.; Sai, Y. Padma

doi:10.1109/isco.2016.7727138

Cited by 7 publications

(2 citation statements)

References 3 publications

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“…G. Surekha et al, designed a 7T SRAM cell [28], consisting of seven transistors and two storage nodes.…”

Section: T Sram Cell Designmentioning

confidence: 99%

“…(i) Conventional 6T[13]. (ii) 7T[28]. (iii) Schmitt trigger-based 8T[29].6.2 | SECOND CATEGORY OF REVIEWED RHBD SRAM CELLS 6.2.1 | QUATRO -10T, WE-QUATRO designs (Year: December 2009; September 2017)In[30], Jahinuzzaman et al proposed a quadruple 10 transistor radiation tolerant robust SRAM cell, QUATRO-10T that provides differential read operation and exhibits larger SNM and less leakage current.…”

mentioning

confidence: 99%

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A comprehensive review and side channel attack analysis on radiation-tolerant SRAM cells for aerospace, terrestrial and nuclear applications

Sengupta,

Yadav

2024

Preprint

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In memory, single event upset (SEU) and single event multiple node upset (SEMNU) have become the principal problems during the past four decades. Significant dependability issues arise from these upsets in a variety of applications such as space, terrestrial, military, and healthcare sector. The use of scaled on-chip memory devices to store private and sensitive data has grown dramatically in the last several years across all the sectors. Memory devices are seriously at risk from non-invasive side-channel assaults (SCAs), which extract secret and sensitive information as well as during SEU/SEMNU, which may flip stored secret and sensitive information. This article presents the history behind the emergence of radiation-hardened circuits and survey of several techniques to mitigate the impact of radiation over the past few decades along with SCA based on leakage power analysis. By educating the researchers on two crucial on-chip memory issues—radiation effect SEU/SEMNU and SCA—this work seeks to accelerate co-design efforts.

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“…G. Surekha et al, designed a 7T SRAM cell [28], consisting of seven transistors and two storage nodes.…”

Section: T Sram Cell Designmentioning

confidence: 99%

mentioning

confidence: 99%

A comprehensive review and side channel attack analysis on radiation-tolerant SRAM cells for aerospace, terrestrial and nuclear applications

Sengupta,

Yadav

2024

Preprint

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Stability and Power Analysis of Read Decoupled 8T SRAM Cell

Bansal

Tomar

2021

Advances in Intelligent Systems and Computing

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WITHDRAWN: Designing of 64 K Bit SRAM using increased substrate bias 7 T SRAM cell

Surekha¹,

Balaji

Sai³

2020

Materials Today: Proceedings

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Stability analysis of 7T-SRAM cell

Cited by 7 publications

References 3 publications

A comprehensive review and side channel attack analysis on radiation-tolerant SRAM cells for aerospace, terrestrial and nuclear applications

A comprehensive review and side channel attack analysis on radiation-tolerant SRAM cells for aerospace, terrestrial and nuclear applications

Stability and Power Analysis of Read Decoupled 8T SRAM Cell

WITHDRAWN: Designing of 64 K Bit SRAM using increased substrate bias 7 T SRAM cell

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Stability analysis of 7T-SRAM cell

Cited by 7 publications

References 3 publications

A comprehensive review and side channel attack analysis on radiation-tolerant SRAM cells for aerospace, terrestrial and nuclear applications

A comprehensive review and side channel attack analysis on radiation-tolerant SRAM cells for aerospace, terrestrial and nuclear applications

Stability and Power Analysis of Read Decoupled 8T SRAM Cell

WITHDRAWN: Designing of 64 K Bit SRAM using increased substrate bias 7 T SRAM cell

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WITHDRAWN: Designing of 64 K Bit SRAM using increased substrate bias 7 T SRAM cell