Stability Analysis of Fourth-Order Charge-Pump PLLs Using Linearized Discrete-Time Models

Dynamics of charge‐pump phase‐locked loops

“…Although these standard linear models provide some empirical rules for practical design, they do not accurately reflect the true behavior of the system and obviously cannot explain the nonlinear dynamics. Accordingly, many authors have developed nonlinear models for the CP‐PLL, which more accurately reflect the nature of the phase frequency detector. It should be noted that various behavioral models have also been proposed .…”

Linearized discrete-time model of higher order Charge-Pump PLLs

“…Van Paemel [2], Hedayat [3] and Co [4] have given nonlinear models for second order loops. Hanumolu [5] and Wang [6] have analysed third order CP-PLLs while Guermandi [7] and Yao [8] have studied fourth order CP-PLLs. In the present work we consider quite general nth order CP-PLLs.…”

Modeling the High-Frequency Degradation of Phase/Frequency Detectors

“…1, quickly become the dominant choice of most integrated-circuit designers for many signal synchronization processings due to their superior performance. To gain understanding and insight of loop dynamics, many CPLL analyses adopting various models and different levels of approximations have been conducted [1]- [6]. Although exact analyses employing discrete-time transfer functions [1], [2], [6], state equations [3], and a nonlinear phase/frequency detector (PFD) model [4] are accurate, the tasks are usually formidable, particularly for practical third-order or more implementations.…”

“…To gain understanding and insight of loop dynamics, many CPLL analyses adopting various models and different levels of approximations have been conducted [1]- [6]. Although exact analyses employing discrete-time transfer functions [1], [2], [6], state equations [3], and a nonlinear phase/frequency detector (PFD) model [4] are accurate, the tasks are usually formidable, particularly for practical third-order or more implementations. A continuous-time linear model, under a certain constraint such as keeping the bandwidth of the phase-locked loop (PLL) relatively lower than the PFD update frequency, continues to be of use to many PLL designers.…”