Stability and Performance Analysis of Low Power 6T SRAM Cell and Memristor Based SRAM Cell using 45NM CMOS Technology

Kumar, Ashish; Suman, B. Shaiwal; Sarkar, Chayan; Kushwaha, Dinesh

doi:10.1109/icrieece44171.2018.9009119

Cited by 9 publications

(1 citation statement)

References 5 publications

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“…During the read operation, the two bit-lines are pre-charged and when WL is enabled, one of the bit-lines will discharge through the access transistor and pull-down transistor depending on the stored logic levels. Although two bit-lines are not required, they are frequently used to increase noise margins by providing both the signal and its inverse [17].…”

Section: Literature Reviewmentioning

confidence: 99%

Design of High-Speed Dual Port 8T SRAM Cell with Simultaneous and Parallel READ-WRITE Feature

Aura

Huq

Biswas

2022

Int. j. electr. comput. eng. syst. (Online)

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An innovative 8 transistor (8T) static random access memory (SRAM) architecture with a simple and reliable read operation is presented in this study. LTspice software is used to implement the suggested topology in the 16nm predictive technology model (PTM). Investigations into and comparisons with conventional 6T, 8T, 9T, and 10T SRAM cells have been made regarding read and write operations' delay and power consumption as well as power delay product (PDP). The simulation outcomes show that the suggested design offers the fastest read operation and PDP optimization overall. Compared to the current 6T and 9T topologies, the noise margin is also enhanced. Finally, the comparison of the figure of merit (FoM) indicates the best efficiency of the proposed design.

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Section: Literature Reviewmentioning

confidence: 99%