Stability degree of switches with finite buffers and non-negligible round-trip time☆

Gusat, Mitch; Audigier, François; Gramsamer, Ferdinand; Luijten, Ronald P.; Minkenberg, Cyriel; Verhappen, M.

doi:10.1016/s0141-9331(03)00025-5

Cited by 7 publications

(3 citation statements)

References 23 publications

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“…• For any nonblocking CIOQ architecture, whether shared-memory or buffered-crossbar, the total buffer requirement to support any traffic pattern scales quadratically with N and linearly with round-trip time: O(N 2 × RTT). 16 The increasing line speed and the increasing physical size of switch systems imply a long intrafabric round-trip time, which, combined with the growing port count, drives the buffer requirements up. Packet routing switch architecture Figure 2 is a conceptual block diagram of our proposed CICQ architecture, which we will describe in the context of a communications switch.…”

Section: Why Cicq?mentioning

confidence: 99%

“…It uses an additional 2-bit subport destination (SPD) identifier to address subports. To reduce overhead, we define four 16 The fabric interface implementation is a combined ingress-egress chip that connects to any network processor unit compliant with the NPF Streaming Interface standard (NPFSI). The system segments the data stream entering the switch fabric into fixedsized packets of either 64 or 80 bytes.…”

Section: System Architecture Requirements and Overviewmentioning

confidence: 99%

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A four-terabit packet switch supporting long round-trip times

et al. 2003

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Section: Why Cicq?mentioning

confidence: 99%

Section: System Architecture Requirements and Overviewmentioning

confidence: 99%

A four-terabit packet switch supporting long round-trip times

et al. 2003

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“…With buffered crossbars the scaling bottleneck lies in the aggregate buffer requirements, which scale quadratically with the number of ports [7].…”

Section: Introductionmentioning

confidence: 99%

Speculative Flow Control for High-Radix Datacenter Interconnect Routers

Minkenberg

Gusat

2007

2007 IEEE International Parallel and Distributed Processing Symposium

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Applying search algorithms to obtain the optimal configuration of nDT torus nodes

Andújar‐Muñoz

Villar-Ortiz

Sánchez

et al. 2017

Concurrency and Computation

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SummaryAn nDT torus is a topology where each node comprises 2 identical (n+1)‐port communication cards interconnected by 1 port. By using the current switches or communication cards, this node architecture allows to build torus networks having a greater number of dimensions than networks including only 1 card per node. There are multiple ways to use the ports of the 2 cards to connect a node to other nodes on the nDT torus, and therefore, checking all the configurations is only an affordable problem for small values of n. In this paper, we use artificial intelligence and data mining techniques to obtain the optimal port configuration of all the nodes in the network. We include a performance evaluation that shows nDT torus effectively increases the performance compared with the equivalent torus in resources, with synthetic and application trace–based workloads. We also apply these techniques to 3DT and 5DT tori to confirm the increase in the number of dimensions that does not affect to performance of the nDT torus.

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Stability degree of switches with finite buffers and non-negligible round-trip time☆

Cited by 7 publications

References 23 publications

A four-terabit packet switch supporting long round-trip times

A four-terabit packet switch supporting long round-trip times

Speculative Flow Control for High-Radix Datacenter Interconnect Routers

Applying search algorithms to obtain the optimal configuration of nDT torus nodes

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