Stable thin film encapsulation of acceleration sensors using polycrystalline silicon as sacrificial and encapsulation layer

Höchst, Arnim; Scheuerer, R.; Stahl, H.; Fischer, F.; Metzger, Lars; Reichenbach, Ralf; Lärmer, Franz; Kronmüller, S.; Watcham, S.; Rusu, Cristina; Witvrouw, Ann; Gunn, R.

doi:10.1016/j.sna.2003.12.020

Cited by 26 publications

(12 citation statements)

References 7 publications

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“…Polysilicon of different thicknesses was deposited to seal the device with the porous polysilicon shell. The device was successfully vacuum-sealed by a polysilicon layer as thin as 1000 Å, far thinner than any other reports [5]- [14], [29]. The amount of the polysilicon sealing material, which may have passed through the porous polysilicon shell and landed on the surfaces inside the cavity, was measured on the silicon nitride thin film on the silicon wafer.…”

Section: A Encapsulation Of Pirani Gauge By Porous Polysilicon Shellmentioning

confidence: 95%

On-Wafer Monolithic Encapsulation by Surface Micromachining With Porous Polysilicon Shell

Kim

2007

J. Microelectromech. Syst.

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Abstract-In this paper, we present a novel microfabrication technique that solves the main problems of existing monolithic on-chip encapsulation methods for polysilicon surface micromachining. The encapsulation technique includes the formation of a nanoporous polysilicon shell, creation of a cavity by removing the sacrificial layer through the pores in the shell, and sealing the cavity at a low pressure. Formed porous by postdeposition electrochemical etching on top of a sacrificial layer, the porous polysilicon is thick enough to free-stand when released, unlike the previously reported as-deposited permeable polysilicon. Benefiting from the dense pores through the polysilicon layer, the sacrificial material was removed in just one minute, and the vacuum sealing was achieved by a low-pressure chemical vapor deposition polysilicon as thin as 1000 Å with no sealing material detected inside the cavity. The pressure inside the sealed cavity, measured by an encapsulated polysilicon Pirani gauge, was around 130 mTorr and showed no noticeable leak ( 30 mTorr) over one year. To showcase the applicability, the proposed process was demonstrated through the common Multiuser MEMS Process (MUMPs) foundry service.[1713]

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Section: A Encapsulation Of Pirani Gauge By Porous Polysilicon Shellmentioning

confidence: 95%

On-Wafer Monolithic Encapsulation by Surface Micromachining With Porous Polysilicon Shell

Kim

2007

J. Microelectromech. Syst.

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“…Encapsulation Sealing Figure 1: Schematic representation of a thin-film encapsulated MEMS device Several thin-film encapsulation techniques, using different materials and processes, are reported in the literature [1][2][3][4][5][6], each having their distinctive pros and cons. However, a majority of the reported techniques have shortcomings like being costly and exclusive, requiring high temperature processing, employing less reliable materials, involving process complexity, etc.…”

Section: Memsmentioning

confidence: 99%

“…also require a stable and controlled environment, like vacuum for instance, for reliable operation. These challenging demands are usually fulfilled by means of packaging MEMS devices on the wafer-level using either wafer bonding [1,2] or thin-film chip-scale encapsulation [1][2][3][4][5][6], also known as zero-level packaging. Typical requirements for wafer-level MEMS packaging are low cost processing, CMOS compatibility (in terms of materials employed, process development and device compatibility), hermeticity, robustness, stability, good sealing characteristics and an ability to withstand harsh environments.…”

Section: Introductionmentioning

confidence: 99%

Robust Wafer-Level Thin-Film Encapsulation of Microstructures using Low Stress PECVD Silicon Carbide

Rajaraman¹,

Pakula²,

Pham

et al. 2009

2009 IEEE 22nd International Conference on Micro Electro Mechanical Systems

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This paper presents a new low-cost, CMOS-compatible and robust wafer-level encapsulation technique developed using a stress-optimised PECVD SiC as the capping and sealing material, imparting harsh environment capability. This technique has been applied for the fabrication and encapsulation of a wide variety of surface-and thin-SOI microstructures that included microcavities, RF switches and various accelerometers. Advantages of our technique are its versatility, smaller footprint, reduced chip thickness and process complexity, post-CMOS batch processing capability and added functionality due to the possibility of integrating additional electrodes for MEMS. Besides fabrication details, this work also discusses related design aspects for large-area MEMS and demonstrates the encapsulation results. Successfully encapsulation of device geometries as large as 955x827.m2 has been achieved.

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“…Membranes find applications in microfluidics and microphone applications. Finally resonators [2] can be used as sensors for temperature [3], viruses [4], gas [5] or particles [6], motion [7], pressure [8] and in many other applications such as oscillators [9,10].…”

Section: Introductionmentioning

confidence: 99%

Failure modes of Wafer Level Thin Film MEMS packages during wafer thinning

Zaal

Driel

Zhang

2010

2010 11th International Thermal, Mechanical &Amp; Multi-Physics Simulation, and Experiments in Microelectronics and Microsystem

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Stable thin film encapsulation of acceleration sensors using polycrystalline silicon as sacrificial and encapsulation layer

Cited by 26 publications

References 7 publications

On-Wafer Monolithic Encapsulation by Surface Micromachining With Porous Polysilicon Shell

On-Wafer Monolithic Encapsulation by Surface Micromachining With Porous Polysilicon Shell

Robust Wafer-Level Thin-Film Encapsulation of Microstructures using Low Stress PECVD Silicon Carbide

Failure modes of Wafer Level Thin Film MEMS packages during wafer thinning

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