Stack Sizing for Optimal Current Drivability in Subthreshold Circuits

The dominance of leakage currents in circuit design has been impelled by steady downscaling of MOSFET into nanometer regime, and has become a significant component of total IC power dissipation. The issue is further aggravated with the inability to gauge the tolerance of process parameters around their nominal value. Consequently, the drive to improve the static power prediction has enticed accurate and reliable modeling of leakage current, specifically for ultralow power applications. In contrast to gate-and band-to-band-tunneling leakages, subthreshold leakage exhibits high susceptibility to process variations and hence has been considered for variability modeling. Fluctuations in the device electrical and geometry parameters result in a wider distribution of subthreshold leakage current. Hence, taking into account stacking effect, an analytical variability model to estimate subthreshold leakage power in subthreshold circuits, in the presence of threshold voltage variations is proposed. Further, the impact of threshold voltage variability on subthreshold leakage power is modeled in conjunction with simultaneous variations in gate length and width. The leakage power variability is characterized by model-generated distributions obtained using Monte Carlo analysis and validated against SPICE simulations. The proposed model is about 700× computationally faster than SPICE simulations with mean error being less than 0.19%. KEYWORDSanalytical variability modeling, device stacking, Monte Carlo analysis, subthreshold design, subthreshold leakage power, variability-aware design 739 Int J Circ Theor Appl. 2020;48:739-749.wileyonlinelibrary.com/journal/cta

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“…The subthreshold leakage current of NMOS transistors, M1 and M2 of a NAND gate, as shown, in Figure 2 is given by 24 :…”

Section: Subthreshold Leakage Power Variability Model For Nmos Stackmentioning

confidence: 99%

Process‐induced variability modeling of subthreshold leakage power considering device stacking

Reddy

Harish

2020

Circuit Theory & Apps

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“…By replacing and into , the following expression for V X is obtained:

V_{X} \approx \frac{n_{N} V_{T} ([], ln ((), \frac{W_{N, 1}}{W_{N, 2}}) - ln ((), a_{x})) + λ_{D}^{N} V_{O U T}}{n_{N} V_{T} b_{x} + 2 λ_{D}^{N} + λ_{B}^{N}},

where W N ,1 and W N ,2 are the channel width of transistors M N ,1 and M N ,2 , respectively. As demonstrated in , only negligible improvements in terms of current driving are achieved by considering skewed sizing for transistors in the stack. For this reason, the condition W N ,1 = W N ,2 is assumed for the rest of this analysis.…”

Section: Logic Gates With Stacked Transistorsmentioning

confidence: 99%

“…For this reason, the condition W N ,1 = W N ,2 is assumed for the rest of this analysis. Such a choice also reduces the design complexity . With reference to the upper transistor M N ,1 , the driving current flowing in the stack, during the H‐to‐L output transition, can be expressed as

I_{stack} \approx β_{N, 1} e^{\frac{V_{D D} - V_{X} - V_{T H, N (1)}}{n_{N} V_{T}}} .

…”

Section: Logic Gates With Stacked Transistorsmentioning

confidence: 99%

Gate‐level body biasing for subthreshold logic circuits: analytical modeling and design guidelines

Albano

Lanuzza

Taco

et al. 2014

Circuit Theory & Apps

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Summary Gate‐level body biasing provides an attractive solution to increase speed and robustness against process and temperature variations while maintaining energy efficiency. In this paper, the behavior of basic logic gates, designed according to the proposed design technique, is analytically examined with the main purpose of furnishing important guidelines to design efficient subthreshold digital circuits. Our modeling has been fully validated by comparing the predicted results with SPICE simulations performed for a commercial 45‐nm complementary metal oxide semiconductor technology. Considering process, temperature and loading capacitance variations, the delay of an inverter is predicted with a maximum error lower than 16.5%. Even better results are obtained when our modeling is applied to more complex logic gates. Under process, loading capacitance and temperature variations, the delay of NAND2 and NOR2 logic gates is always predicted with an error below 10%. Good agreement between the predicted and simulated results makes our modeling a valuable support during the circuit design phase. Copyright © 2014 John Wiley & Sons, Ltd.

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“…In [14], a framework for choosing the optimal transistor-stack sizing factors in terms of current drivability is proposed for subthreshold design. A closed-form solu tion for the proposed sizing of transistors in a stack is also derived.…”

Section: Transistor Sizing and Delay Compensation Techniquesmentioning

confidence: 99%

“…In [15], the use of Logical Effort in the subthreshold region was explored. However, the impact of INWE on transistor sizing for the subthreshold operation was not considered in [14] and [15].…”

Section: Transistor Sizing and Delay Compensation Techniquesmentioning

confidence: 99%

Designing faster CMOS subthreshold circuits using transistor sizing and paralled transistor stacks

Nabavi¹

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Stack Sizing for Optimal Current Drivability in Subthreshold Circuits

Cited by 22 publications

References 5 publications

Process‐induced variability modeling of subthreshold leakage power considering device stacking

Process‐induced variability modeling of subthreshold leakage power considering device stacking

Gate‐level body biasing for subthreshold logic circuits: analytical modeling and design guidelines

Designing faster CMOS subthreshold circuits using transistor sizing and paralled transistor stacks

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