Utilizing reverse short-channel effect for optimal subthreshold circuit design

The impact of the Reverse Short Channel Effect (RSCE) on device current is stronger in the subthreshold region due to the reduced Drain-Induced-Barrier-Lowering (DIBL) and the exponential dependency of current on threshold voltage. This paper describes a device size optimization method for subthreshold circuits utilizing RSCE to achieve high drive current, low device capacitance, less sensitivity to random dopant fluctuations, and better subthreshold swing. Simulation results using ISCAS benchmark circuits show that the critical path delay and power consumption can be improved by up to 10.4% and 34.4%, respectively.

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Abstract-Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors in the subthreshold region are significantly different from those in stronginversion. This presents new challenges in design optimizationparticularly in complex gates with stacks of transistors. In this paper, we present a framework for choosing the optimal transistor stack sizing factors in terms of current drivability for subthreshold designs. We derive a closed-form solution for the correct sizing of transistors in a stack, both in relation to other transistors in the stack, and to a single device with equivalent current drivability. Simulation results show that our framework provides a performance benefit ranging up to more than 10% in certain critical paths.Index Terms-Subthreshold logic, logical effort, ultra low power design

damping performance in Fig. 3 proves that the proposed switched A low power switched decoupling capacitor circuit is proposed to decap performs more than 8X better than a conventional decap.suppress on-chip resonant supply noise. Compared to previous Under process variation, the change of R value (cc l/(Vdd-VTpanalog techniques, the proposed digital implementation achieves a 9X VT,,)) tracks the change of IDC ( cx Vdd-VTp-VTfl) leading to a process reduction in quiescent power with improved tolerance to PVT insensitive VSW (DCR). Simulation result in Fig. 4 confirms a Vsw variation and tuning capability for optimal switching threshold. variation of less than 8mV across different process corners (+25mV Measurements from a 0.13ptm test chip show an lIX boost in of VT) and temperatures (25-1 10'C). To enable a fine tuning ofVsw, effective decap value and a 9.8dB suppression in resonant supply the R value can also be programmed by turning on different number noise by using the proposed circuit.of MOS devices in the RC filter circuits. The proposed circuit is Introduction designed with a resonant regulation range of 1OMHz-300MHz. On-chip resonant supply noise caused by package inductance and onResonant Noise Measurements chip capacitance poses a severe threat to system performance because A test chip has been fabricated in a 1.2V, 0.13pim CMOS process.of its large magnitude and long duration. The resonant noise, Fig. 5 shows the test chip organization. To generate a resonant typically in the 40-200MHz band, can be excited by a microprocessor supply noise, four 16-bit multipliers with operating frequencies up to loop command or a large current surge during an abrupt start-up or 1.0GHz were synthesized and implemented using standard cell termination [1, 2]. Conventional decoupling capacitors (decaps) are libraries. A clock pattern controller is used to create a gated clock inefficient to suppress resonance because of the large die area and which can produce noise components at lower frequencies. A 16-bit gate leakage consumption. This paper presents a low power digitally clock code is scanned into the controller to set the gated clock controlled switched decap circuit to suppress the resonant noise. pattern. A '1' passes a clock pulse while a '0' masks the clock pulse. Unlike prior work that employs differential amplifiers to sense supply As the examples shown in Fig. 6, a '0101010101010101 ' produces a noise [3], the proposed scheme uses digital circuits for noise detection sub-harmonic noise at 1/2 of the original clock frequency while a to reduce power consumption. A 9X reduction in quiescent power is '0000111100001111' produces sub-harmonic at 1/8 of the clock achieved with improved tolerance to process-voltage-temperature frequency. For testing purposes, we also implemented a simple (PVT) variations and added tuning capability for switching threshold. noise injection circuit that generates supply noise at a given clock The proposed circuit can be embedded into digital IC's without frequency. Different values of swi...