Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing

Keane, J.; Eom, Hanyong; Kim, Tae‐Hyoung; Sapatnekar, S.; Kim, C.

doi:10.1109/dac.2006.229226

Cited by 25 publications

(22 citation statements)

References 4 publications

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“…2 In this document, we may use super/subthreshold words in place of super/subthreshold-voltage for brevity. groups in the VLSI and digital electronics area who have shown promising results [17,11,13,8,9,22]. Figure 3 reveals another difference between the two regions: unlike in the superthreshold region, voltage scaling does not necessarily improve energy efficiency over the entire subthreshold region.…”

Section: Subthreshold Voltage Operationmentioning

confidence: 99%

A low-power parallel design of discrete wavelet transform using subthreshold voltage technology

Henry

Haider

Nazhandali

2008

Proceedings of the 2008 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

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Section: Subthreshold Voltage Operationmentioning

confidence: 99%

A low-power parallel design of discrete wavelet transform using subthreshold voltage technology

Henry

Haider

Nazhandali

2008

Proceedings of the 2008 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

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“…It is implied that standard cell timing could be improved using the mentioned design techniques. The concept of sub-threshold logical effort for complex gate sizing is presented in [9]. Particularly interesting is a closed form current equation derived for stacked transistors in relation to other transistors in the same stack.…”

Section: Sub-threshold Cell Sizing Methodologymentioning

confidence: 99%

“…Particularly interesting is a closed form current equation derived for stacked transistors in relation to other transistors in the same stack. Compared to [3,4,9], our sizing approach focuses on narrowing the current/delay distribution spread and on increasing the performance through a new balancing theory that slows down fast transistors and vice versa. In [8], the transistor reverse short channel effect (RSCE) is used for device sizing optimization, where the channel length is increased to have an optimal threshold voltage which makes the transistors have a higher current, be less sensitive to random variations, and to have a smaller area.…”

Section: Sub-threshold Cell Sizing Methodologymentioning

confidence: 99%

“…where is a technology fitting parameter and  is the DIBL effect coefficient [9]. To simplify the calculation of the equivalent transistor size of the stack, the length of each transistor in the stack is held fixed.…”

Section: Stack Sizing Modelmentioning

confidence: 99%

“…Unlike conventional "super-threshold" cell sizing methods [8,9], the proposed balancing-based sizing method focuses on the statistical distribution of the drain-source current, rather than the current itself. In the proposed approach, the variation of the current is taken into consideration when sizing the standard cells by balancing the mean current of the equivalent N and P networks.…”

Section: Introductionmentioning

confidence: 99%

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Sub-Threshold Standard Cell Sizing Methodology and Library Comparison

Liu

Gyvez

Ashouei

2013

JLPEA

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Abstract:Scaling the voltage to the sub-threshold region is a convincing technique to achieve low power in digital circuits. The problem is that process variability severely impacts the performance of circuits operating in the sub-threshold domain. In this paper, we evaluate the sub-threshold sizing methodology of [1,2] on 40 nm and 90 nm standard cell libraries. The concept of the proposed sizing methodology consists of balancing the mean of the sub-threshold current of the equivalent N and P networks. In this paper, the equivalent N and P networks are derived based on the best and worst case transition times. The slack available in the best-case timing arc is reduced by using smaller transistors on that path, while the timing of the worst-case timing arc is improved by using bigger transistors. The optimization is done such that the overall area remains constant with regard to the area before optimization. Two sizing styles are applied, one is based on both transistor width and length tuning, and the other one is based on width tuning only. Compared to super-threshold libraries, at 0.3 V, the proposed libraries achieve 49% and 89% average cell timing improvement and 55% and 31% power delay product improvement at 40 nm and 90 nm respectively. From ITC (International Test Conference 99) benchmark circuit synthesis results, at 0.3 V the proposed library achieves up to 52% timing improvement and 53% power savings in the 40 nm technology node. OPEN ACCESSJ. Low Power Electron. Appl. 2013, 3 234

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