Stack-through silicon via dynamic power consumption optimization in three-dimensional integrated circuit

Abstract

Stack-through silicon via (TSV) used in three-dimensional integrated circuit has good temperature and heat transfer characteristics. A novel model for optimizing the dynamic power consumption based on stacked-TSV is proposed in this paper, in which delay, area and minimum aperture are comprehensively considered. After extracting single TSV parasitic electrical parameters, we analyze the influences of TSV size on multilayer TSV power consumption and delay performance, thereby building the hierarchical reduction TSV structure step by step. Moreover, the influences of TSV height and thickness of oxide layer are discussed. Results show that the model can significantly improve the dynamic power consumption at the expense of little delay. The power consumption optimization reduction is up to 19.52% with 5% delay penalty.

Parasitic effects of air-gap through-silicon vias in high-speed three-dimensional integrated circuits

“…Physical constraints and technological challenges beyond 22-nm node now set back the further development of Moore's Law of scaling the feature size of transistor. [1][2][3][4][5][6][7] The interconnect performance becomes a key challenge to achieving the overall performance of a chip. Compared with conventional circuits, through-silicon vias (TSVs) for vertical interconnection are able to achieve shorter wiring paths, higher interconnect densities, and smaller foot prints.…”

“…Therefore, the technology of three-dimensional integrated circuits (3D ICs) has the potential to significantly improve the system functionality and performance. [1][2][3][4][5][6][7] With the rapid development of silicon technologies, the operating frequency of 3D ICs has been progressively expanded into millimeter-wave (mmW) and terahertz (0.1-10 THz) regions. [8] The heterogeneous integration and high operating speed make the signal integrity (SI) and the coupling noise induced by massive TSVs be major concerns for 3D IC systems.…”