Stacked Gate-All-Around Nanosheet pFET with Highly Compressive Strained Si_1-xGe_x Channel

In-line Raman spectroscopy for gate-all-around nanosheet device manufacturing

“…Even more important is strain metrology for pFET devices particularly because complex strain engineering approaches are developed to boost hole mobility. 4 While the electron mobility in nanosheet devices is much better compared to finFETs due to the channel orientation the intrinsic tensile strain induced by the sacrificial sheets, the hole mobility in the same channels is rather low. Therefore, compressive Si ð1−xÞ Ge x channels are desired.…”

“…Front-up dual processing is complex and costly, hence a iGe channel last approach has been proposed recently. 4 The innovative part starts post Si ð1−xÞ Ge x channel release and the method relies on trimming down the Si channels to a thickness of about 2 nm before growing a pseudomorphic Si ð1−xÞ Ge x cladding all around the channel. In-line strain monitoring with Raman spectroscopy at multiple processing steps within this flow (e.g., after trimming and after Si ð1−xÞ Ge x growth) will be an invaluable addition to ensure successful development and consistent high volume manufacturing of these next-generation GAA nanosheet devices.…”

“…Overcoming these challenges requires either complex and costly manufacturing schemes or innovative strain engineering approaches. 3,4 No matter which integration scheme is pursued, the complex manufacturing process, particularly related to the channels and their immediate environment, requires tight specification limits and hence additional, more advanced, and novel in-line metrology capabilities compared to previous transistor architectures. Specifically, monitoring and controlling strain at such small scales and within intricate nanoscale device structures is a new challenge and a suitable nondestructive and fast in-line technique is critical for successful research and development and manufacturing.…”

“…Beam diameters of ∼5 nm allow mapping of channel strain even in aggressively scaled FETs with channel lengths of <20 nm. [4][5][6][7] However, TEM techniques are time-consuming, destructive, and require sample preparation, which may influence strain characteristics.…”

Electrical Properties of HfO2 on Si1–xGex Substrates Pretreated Using a Y Precursor with and without Subsequent Oxidant Pulsing

“…The mixing of single-crystalline Si channels with Ge has been extensively employed as the most practical and promising method of increasing the carrier mobility of high-performance metal–oxide–semiconductor field-effect transistors (MOSFETs) . Owing to the complete compatibility of epitaxial Si 1– x Ge x films with recent Si device integration processes, these films can be easily employed even for the most recent gate-all-around MOSFETs with sub-3 nm technology nodes. − Moreover, HfO 2 -based films have been extensively studied as a high- k gate dielectric film because of their excellent thermal stability and relatively high dielectric constant. − However, the most critical problem hindering the practical use of Si 1– x Ge x films is their Si 1– x Ge x /high- k gate dielectric interfacial characteristics, which must be improved to a level similar to that of the conventional high- k /Si interface. The poor electrical characteristics of high- k /Si 1– x Ge x films are believed to stem from the formation of thermodynamically unstable Ge sub oxides (GeO x ) at the high- k /Si 1– x Ge x interface. ,,, …”