Standard and ROM-based synthesis of FSMs with control flow checking capabilities

Wendling, X.; Rochet, R.; Leveugle, Régis

doi:10.1109/vtest.1996.510839

Proceedings of 14th VLSI Test Symposium

DOI: 10.1109/vtest.1996.510839

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Standard and ROM-based synthesis of FSMs with control flow checking capabilities

X. Wendling¹,

R. Rochet²,

Régis Leveugle³

Abstract: ISBN: 0818673044This paper deals with the detection of sequencing errors in finite state machines. Several control-flow checking methods, implemented in an automatic synthesis tool, are presented. The contribution of this paper lies in that these methods are introduced in the ROM-based architecture, and compared to equivalent methods available in the standard synthesis flow

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Cited by 2 publications

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ROM-based synthesis of fault-tolerant controllers

Wendling¹,

Rochet²,

Leveugle³

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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ISBN: 0818675454Fault tolerance has become a major concern in the design of VLSI systems. It is especially needed in finite state machines (FSMs) where a failure can have huge consequences on the whole circuit behavior. Several methods have been proposed in the last few years to implement such features in FSMs synthesized on standard cells. At the same time, considering circuit cost, performances and design efficiency, it has been shown that large controllers should rather be synthesized on a particular ROM-based architecture. The work presented here has consisted in studying, implementing and evaluating fault tolerance methods in FSMs in a ROM-based synthesis flow

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ROM-based synthesis of fault-tolerant controllers

Wendling¹,

Rochet²,

Leveugle³

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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Automatic and optimized synthesis of dataparts with fault detection or tolerance capabilities

Wendling¹,

Chauvet²,

Revéret³

et al.

1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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Standard and ROM-based synthesis of FSMs with control flow checking capabilities

Cited by 2 publications

References 8 publications

ROM-based synthesis of fault-tolerant controllers

ROM-based synthesis of fault-tolerant controllers

Automatic and optimized synthesis of dataparts with fault detection or tolerance capabilities

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