STAP: An Architecture and Design Tool for Automata Processing on Memristor TCAMs

Abstract

Accelerating finite-state automata benefits several emerging application domains that are built on pattern matching. In-memory architectures, such as the Automata Processor (AP), are efficient to speed them up, at least for outperforming traditional von-Neumann architectures. In spite of the AP’s massive parallelism, current APs suffer from poor memory density, inefficient routing architectures, and limited capabilities. Although these limitations can be lessened by emerging memory technologies, its architecture is still the major source of huge communication demands and lack of scalability. To address these issues, we present STAP , a Scalable TCAM-based architecture for Automata Processing . STAP adopts a reconfigurable array of processing elements, which are based on memristive Ternary CAMs (TCAMs), to efficiently implement Non-deterministic finite automata (NFAs) through proper encoding and mapping methods. The CAD tool for STAP integrates the design flow of automata applications, a specific mapping algorithm, and place and route tools for connecting processing elements by RRAM-based programmable interconnects. Results showed 1.47× higher throughput when processing 16-bit input symbols, and improvements of 3.9× and 25× on state and routing densities over the state-of-the-art AP, while preserving 10 4 programming cycles.

Desafios para a Computação Energeticamente Eficiente

“…• aproveitar oportunidades de computação com tecnologias alternativas, que embora garantam baixa energia, trazem outro conjunto de problemas a serem resolvidos [ Carro 2022];…”

YARB: a Methodology to Characterize Regular Expression Matching on Heterogeneous Systems

“…ASIC-based engines: This class mainly exploits the inmemory approach similar to the FPGA-embedding in different structures such as Content Addressable Memories (CAMs) [35], [41], or other special memories [19], [32], [34]. Besides, others devise DSAs, but they provide simulation results only [21].…”

Enabling Efficient Regular Expression Matching at the Edge through Domain-Specific Architectures

“…We analyze the State of the Art of REs matching hardware solutions. On the one hand, many embed the REs/automata either in the reconfigurable fabric or in special memories [16], [17], while others exploit SW-programmable DSAs [14], [18]. Given the limited resources we exclude embedding solutions; therefore, we build our system design approach for HIDS on the open DSA CICERO [14] that features flexibility for pattern detection and specialization for low latency.…”