State-based real-time analysis of SDF applications on MPSoCs with shared communication resources

Fakih, Maher; Grüttner, Kim; Fränzle, Martin; Rettberg, Achim

doi:10.1016/j.sysarc.2015.04.005

Cited by 5 publications

(7 citation statements)

References 30 publications

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“…In the study by Fakih et al [13], a tool named sdf2ta has been introduced for analyzing timing bounds of SDF graphs. The tool takes an SDF graph defined using the tool SDF3 and a hardware model defined separately, and automatically generates an Uppaal timed-automata model.…”

Section: Related Workmentioning

confidence: 99%

How to Efficiently Build a Front-End Tool for UPPAAL: A Model-Driven Approach

Schivo

Yildiz

Ruijters

et al. 2017

Dependable Software Engineering. Theories, Tools, and Applications

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We propose a model-driven engineering approach that facilitates the production of tool chains that use the popular model checker Uppaal as a back-end analysis tool. In this approach, we introduce a metamodel for Uppaal's input model, containing both timed-automata concepts and syntax-related elements for C-like expressions. We also introduce a metamodel for Uppaal's query language to specify temporal properties; as well as a metamodel for traces to interpret Uppaal's counterexamples and witnesses. The approach provides a systematic way to build software bridging tools (i.e., tools that translate from a domainspecific language to Uppaal's input language) such that these tools become easier to debug, extend, reuse and maintain. We demonstrate our approach on five different domains: cyber-physical systems, hardwaresoftware co-design, cyber-security, reliability engineering and software timing analysis. IntroductionUppaal [3] is a leading model checker for real-time systems, allowing one to verify automatically whether a system meets its timing requirements. Uppaal and its extensions have been applied to a large number of domains, ranging from communication protocols [28], over planning [4] to systems biology [31]. As such, Uppaal is a popular back-end for various other real-time analysis tools, such as ANIMO [31], sdf2ta [13] and STATE [19]. Typically such tools take their inputs in a domain-specific language (DSL) and translate these inputs into timed automata, which are then fed into Uppaal to perform the analysis. In this way, domain experts can write their models in a DSL that they are familiar with, while still using Uppaal's powerful analysis algorithms behind the scenes.A disadvantage of this approach is, however, that the tools that translate from a DSL to Uppaal's input language, i.e., software bridging tools, are often implemented ad hoc, and hence difficult to debug, reuse, extend and maintain.

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Section: Related Workmentioning

confidence: 99%

How to Efficiently Build a Front-End Tool for UPPAAL: A Model-Driven Approach

Schivo

Yildiz

Ruijters

et al. 2017

Dependable Software Engineering. Theories, Tools, and Applications

View full text Add to dashboard Cite

show abstract

“…1. We enable a state-based real-time analysis (based on [5]) of multiple FSM-SADF applications mapped to an MPSoC platform with shared communication resources. State-based RT analysis methods, deliver very accurate results especially when handling heavy statedepended properties (e.g.…”

Section: Busmentioning

confidence: 99%

“…While such approaches are fast and able to handle large systems, unfortunately they deliver pessimistic results especially when handling state-based bus arbitration protocols typically used in Multi-Processor Systems on a Chip (MPSoCs). In previous work [5] it was shown how far state-based RT analysis of SDFGs on MPSoCs can tighten the results compared to an analytical approach [12].…”

Section: Related Workmentioning

confidence: 99%

“…In [17,18] the authors (similar to the work in [5]) transform a system model which includes an SDFG and a multiprocessor platform to a (priced) timed automata network and utilize an extended model-checker (UPPAAL CORA) to obtain optimal schedules combining optimization goals with optimal throughput and energy consumption.…”

Section: Related Workmentioning

confidence: 99%

“…In this work, we extend a previous model-checking based real-time analysis approach [5] for the analysis of timing bounds for FSM-SADFGs mapped on a shared memory multicore architecture. In [5] only analysis of SDFGs was supported. We utilize timed automata (TA) as a common semantic model to represent worst-case execution times (WCET) of kernels, detectors and shared communication resource.…”

Section: Related Workmentioning

confidence: 99%

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Towards State-Based RT Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication

Stemmer

Fakih

Grüttner

et al. 2017

Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

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CITATIONS 0 READS 22 4 authors, including: Some of the authors of this publication are also working on these related projects: 3Ccar -Integrated Components for Complexity Control in affordable electrified cars View project SAFEPOWER -Safe and secure mixed-criticality systems with low power requirements View project Maher Fakih OFFIS e.V. ABSTRACTScenario-Aware Data-Flow Graphs (SADFGs) were introduced to capture the behavior of embedded applications achieving a good trade-off between expressiveness and analyzability. On the one side, they support the timing analysis of real-time applications, especially those running on MPSoCs, due to the clean separation of computation and communication phases in their executing nodes. On the other side, SADFGs allow the expression of a more dynamic behaviors than Synchronous dataflow graphs by allowing dynamic token-rates of single nodes depending on pre-defined typical scenarios. The fact which leads to more efficiency and better throughput.In this paper, we describe the extension of a previous model-checking based real-time analysis approach to allow the analysis of timing bounds for FSM-SADFGs mapped on a shared memory multiprocessor architecture. We demonstrate our approach on an MPEG decoder application being viable to obtain the worst-case end-to-end latency of its implementation under different scenarios on a 2-tiles MPSoC.

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Formal verification of timed synchronous dataflow graphs using Lustre

Bennour

2021

Journal of Logical and Algebraic Methods in Programming

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State-based real-time analysis of SDF applications on MPSoCs with shared communication resources

Cited by 5 publications

References 30 publications

How to Efficiently Build a Front-End Tool for UPPAAL: A Model-Driven Approach

How to Efficiently Build a Front-End Tool for UPPAAL: A Model-Driven Approach

Towards State-Based RT Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication

Formal verification of timed synchronous dataflow graphs using Lustre

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