State-of-the-Art Circuit Techniques for Low-Jitter Phase-Locked Loops: Advanced Performance Benchmark FOM Based on an Extensive Survey

Bae, Woorham

doi:10.1109/iscas51556.2021.9401059

Cited by 6 publications

(5 citation statements)

References 10 publications

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“…The FoM 𝑗 of PLL_RO and PLL_LC are respectively −226 dB and −224 dB. These two designs are within the state-of-the-art performances [22] and are well in accordance with the goal of this development as presented in table 1.…”

Section: Discussionsupporting

confidence: 77%

Top-down design methodology for a 2 ps rms Jitter at 2.56 GHz of an analog PLL based on Ring and LC Tank Oscillators

Bechetoille¹,

Joly²,

Lemaire³

et al. 2022

J. Inst.

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A top-down methodology is proposed to design Phase-Locked-Loops (PLL) using behavioural and transistor-level simulation in two cases: Ring-Oscillator (RO) and LC Tank Oscillator (LCTO) with the aim to achieve a low-jitter PLL clock generator in 130 nm process. The optimization of these two PLLs is obtained in three steps. The first one is to design a model in Verilog-A of each block with its intrinsic jitter parameter. Each block is simulated alone to verify the nature of its intrinsic jitter: Frequency Modulation jitter (FM jitter) or Phase Modulation jitter (PM jitter). The second step is to place each of these blocks in a global schematic to obtain a full behavioural PLL. In this way, one can study the PLL operation and check the effect of each block's jitter on the PLL output. The third step is to use the intrinsic FM jitter or PM jitter values to simulate at the transistor level of each block individually and then all of them together. To evaluate the loop bandwidth and the loop stability of each of the two PLLs, a linearized PLL is designed using ideal sources. This approach is important to check the compatibility of each block in terms of jitter and bandwidth with respect to the target PLL performance. The optimization results are used to design and produce two PLLs. Measurements of these two are found to have an absolute time jitter of the order of 2 ps rms.

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Section: Discussionsupporting

confidence: 77%

Top-down design methodology for a 2 ps rms Jitter at 2.56 GHz of an analog PLL based on Ring and LC Tank Oscillators

Bechetoille¹,

Joly²,

Lemaire³

et al. 2022

J. Inst.

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show abstract

“…Given the existing correlations and trade-offs between the different LNA specifications, proposed FoMs may hide the strengths and weaknesses of the general topologies to highlight only the strengths of implementations. A similar problem was faced in the field of ADC [5] and PLL [6] design. In the case of ADC design community, a very powerful tool to explore the topologies and their achievable performance is proposed by Boris Murmann in [5].…”

Section: Introductionmentioning

confidence: 95%

Performance benchmark of State-of-the-art Sub-6-GHz wideband LNAs Based on an Extensive Survey

Bouchoucha

Coustans

Barragán

et al. 2023

2023 IEEE International Symposium on Circuits and Systems (ISCAS)

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HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L'archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

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“…This section introduces the advanced PLL design techniques named all-digital PLL (ADPLL), subsampling PLL (SSPLL), injection-locked PLL (ILPLL), and clock-multiplying DLL (MDLL), which are the most popular PLL design techniques in recent ISSCC/VLSI publications, as shown in the survey in Fig. 2 [147].…”

Section: Review Of State-of-the-art Deisgn Techniquesmentioning

confidence: 99%

“…In addition to the break of the assumptions, it does not consider other impact from various factors other than jitter and the power consumption, such as silicon area or process technology node. As a result, new benchmark FOMs are required to complement the limitations of the FOMJ [147].…”

mentioning

confidence: 99%

Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures

Bae

2022

IEEE Access

Self Cite

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A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most powerful indicator to compare and to normalize performance of different PLL designs. Simply, the conventional FOM is based on the jitter-power trade-off. With a few assumptions, theoretically, it provides a fair comparison. However, as the PLL design techniques have advanced, the assumptions have started breaking. Also, it misses performance impacts from some other important factors other than the jitter and the power. As a result, it is expected that the performance comparison with the conventional FOM is not fair enough for some cases. This work reviews the state-of-the-art PLL design techniques and investigates how those techniques conflict with the assumptions of the conventional FOM. In addition, alternate FOMs which complement the conventional FOM are discussed. To capture complex cross-correlation between various factors, the proposed methodology is to find a correlation between the conventional FOM and other factors from extensive performance surveys, along with quantitative analyses.

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State-of-the-Art Circuit Techniques for Low-Jitter Phase-Locked Loops: Advanced Performance Benchmark FOM Based on an Extensive Survey

Cited by 6 publications

References 10 publications

Top-down design methodology for a 2 ps rms Jitter at 2.56 GHz of an analog PLL based on Ring and LC Tank Oscillators

Top-down design methodology for a 2 ps rms Jitter at 2.56 GHz of an analog PLL based on Ring and LC Tank Oscillators

Performance benchmark of State-of-the-art Sub-6-GHz wideband LNAs Based on an Extensive Survey

Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures

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