State space modeling for sub-threshold SRAM stability analysis

Mezhibovsky, Janna; Teman, Adam; Fish, Alexander

doi:10.1109/iscas.2012.6271622

Cited by 5 publications

(2 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Accordingly, several groups have started to focus on developing methods to evaluate the dynamic stability of SRAMs and define dynamic noise margins [2]- [5], [9]- [12], [16]. Dynamic noise analysis most often introduces noise as a time-variant current pulse applied to one or more circuit nodes.…”

Section: Sram Stability Analysismentioning

confidence: 99%

A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMs

Teman

Visotsky²

2015

IEEE Trans. VLSI Syst.

Self Cite

View full text Add to dashboard Cite

Abstract-As memory density continues to grow in modern systems, accurate analysis of SRAM stability is increasingly important to ensure high yields. Traditional static noise margin metrics fail to capture the dynamic characteristics of SRAM behavior, leading to expensive over-design and disastrous under-design. One of the central components of more accurate dynamic stability analysis is the separatrix; however, its straightforward extraction is extremely time-consuming, and efficient methods are either non-accurate or extremely difficult to implement. In this paper, we propose a novel algorithm for fast separatrix tracing of any given SRAM topology, designed with industry standard transistor models in nano-scaled technologies. The proposed algorithm is applied to both standard 6T SRAM bitcells, as well as previously proposed alternative sub-threshold bitcells, providing up to three orders-of-magnitude speedup, as compared to brute force methods. In addition, for the first time, statistical Monte Carlo separatrix distributions are plotted.

show abstract

Section: Sram Stability Analysismentioning

confidence: 99%

A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMs

Teman

Visotsky²

2015

IEEE Trans. VLSI Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…Further state space modeling, including analysis of phase portraits during write operations was provided in [22]. Examples of this analysis are provided in Fig.…”

Section: Dynamic Stability and Dynamic Noise Marginsmentioning

confidence: 99%

Dynamic stability and noise margins of SRAM arrays in nanoscaled technologies

Teman

2014

2014 IEEE Faible Tension Faible Consommation

Self Cite

View full text Add to dashboard Cite

Abstract-SRAM stability is one of the primary bottlenecks of current VLSI system design, and the unequivocal supply voltage scaling limiter. Static noise margin metrics have long been the de-facto standard for measuring this stability and estimating the yield of SRAM arrays. However, in modern process technologies, under scaled supply voltages and increased process variations, these traditional metrics are no longer sufficient. Recent research has analyzed the dynamic behavior and stability of SRAM circuits, leading to dynamic stability metrics and dynamic noise margin definition. This paper provides a brief overview of the limitations of static noise margin metrics and the resulting dynamic stability and noise margin concepts that have been proposed to overcome them.

show abstract