Dynamic stability and noise margins of SRAM arrays in nanoscaled technologies

Abstract

Abstract-SRAM stability is one of the primary bottlenecks of current VLSI system design, and the unequivocal supply voltage scaling limiter. Static noise margin metrics have long been the de-facto standard for measuring this stability and estimating the yield of SRAM arrays. However, in modern process technologies, under scaled supply voltages and increased process variations, these traditional metrics are no longer sufficient. Recent research has analyzed the dynamic behavior and stability of SRAM circuits, leading to dynamic stability metrics and dynamic noise margin definition. This paper provides a brief overview of the limitations of static noise margin metrics and the resulting dynamic stability and noise margin concepts that have been proposed to overcome them.

Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection

“…However, 6T SRAM incur a large area penalty and suffer from high static power consumption, often dominating the power budget and real-estate of these VLSI systems [1], [2]. Moreover, technology scaling has led to a continuous increase in parametric variations, resulting in reduced SRAM noise margins, which ultimately limit the voltage scaling capabilities of these memories [3], [4].…”