Stateful implication logic with memristors

Lehtonen, Eero; Laiho, Mika

doi:10.1109/nanoarch.2009.5226356

Cited by 183 publications

(97 citation statements)

References 3 publications

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“…By using 27 memristors an 8-bit full adder is designed, which requires 184 computational steps to complete its task. This shows about 20 percent faster performance in comparison with the techniques presented in [6] and [7]. …”

Section: Discussionmentioning

confidence: 85%

“…Several implementations were applied for designing 8-bit full adder based on material implication logic. The proposed method in [6] has used 712 computational steps and it also needs 29 memristors for implementing an 8-bit full adder. In [7] 27 memristors are used for implementing an 8-bit full adder with 232 computational steps.…”

Section: -Bit Memristor Based Full Adder Based On Materials Implmentioning

confidence: 99%

“…This full adder is designed with 27 memristors and it needs 184 computational steps for completing its operation which is faster than previous designs [6][7].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Optimized implementation of memristor-based full adder by material implication logic

Teimoory

Amirsoleimani

Shamsi

et al. 2014

2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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Abstract-Recently memristor-based applications and circuits are receiving an increased attention. Furthermore, memristors are also applied in logic circuit design. Material implication logic is one of the main areas with memristors. In this paper an optimized memristor-based full adder design by material implication logic is presented. This design needs 27 memristors and less area in comparison with typical CMOS-based 8-bit full adders. Also the presented full adder needs only 184 computational steps which enhance former full adder design speed by 20 percent.

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Section: Discussionmentioning

confidence: 85%

Section: -Bit Memristor Based Full Adder Based On Materials Implmentioning

confidence: 99%

See 1 more Smart Citation

Optimized implementation of memristor-based full adder by material implication logic

Teimoory

Amirsoleimani

Shamsi

et al. 2014

2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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“…So far a variety of approaches has been proposed for synthesis of logic-in-memory computing circuits, mostly based on material implication (IMP: p → q =p ∨ q) [12], [13] and some using other basic operations [14], [15], [11]. In all these approaches, the target function can only be executed using a certain number of RRAM devices and after a number of operations, which increases rapidly as the size of the function increases.…”

Section: Logic-in-memory Write Trafficmentioning

confidence: 99%

Endurance management for resistive Logic-In-Memory computing architectures

Shirinzadeh

Soeken

Gaillardon

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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Abstract-Resistive Random Access Memory (RRAM) is a promising non-volatile memory technology which enables modern in-memory computing architectures. Although RRAMs are known to be superior to conventional memories in many aspects, they suffer from a low write endurance. In this paper, we focus on balancing memory write traffic as a solution to extend the lifetime of resistive crossbar architectures. As a case study, we monitor the write traffic in a Programmable Logic-in-Memory (PLiM) architecture, and propose an endurance management scheme for it. The proposed endurance-aware compilation is capable of handling different trade-offs between write balance, latency, and area of the resulting PLiM implementations. Experimental evaluations on a set of benchmarks including large arithmetic and control functions show that the standard deviation of writes can be reduced by 86.65% on average compared to a naive compiler, while the average number of instructions and RRAM devices also decreases by 36.45% and 13.67%, respectively.

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“…Physical manifestations of memristors range from thermistors [6] to complex oxide [7][8][9][10][11] and spintronic [12][13][14] materials. A number of possible intriguing applications of memristors have already been discussed including digital memory [15][16][17], neuromorphic systems [18][19][20], adaptive filters [21,22], tunable and reconfigurable metamaterials [11], and others [23][24][25].…”

mentioning

confidence: 99%

Chaotic memristor

et al. 2011

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We suggest and experimentally demonstrate a chaotic memory resistor (memristor). The core of our approach is to use a resistive system whose equations of motion for its internal state variables are similar to those describing a particle in a multi-well potential. Using a memristor emulator, the chaotic memristor is realized and its chaotic properties are measured. A Poincaré plot showing chaos is presented for a simple nonautonomous circuit involving only a voltage source directly connected in series to a memristor and a standard resistor. We also explore theoretically some details of this system, plotting the attractor and calculating Lyapunov exponents. The multi-well potential used resembles that of many nanoscale memristive devices, suggesting the possibility of chaotic dynamics in other existing memristive systems.

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Stateful implication logic with memristors

Cited by 183 publications

References 3 publications

Optimized implementation of memristor-based full adder by material implication logic

Optimized implementation of memristor-based full adder by material implication logic

Endurance management for resistive Logic-In-Memory computing architectures

Chaotic memristor

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