Endurance management for resistive Logic-In-Memory computing architectures

Abstract

Abstract-Resistive Random Access Memory (RRAM) is a promising non-volatile memory technology which enables modern in-memory computing architectures. Although RRAMs are known to be superior to conventional memories in many aspects, they suffer from a low write endurance. In this paper, we focus on balancing memory write traffic as a solution to extend the lifetime of resistive crossbar architectures. As a case study, we monitor the write traffic in a Programmable Logic-in-Memory (PLiM) architecture, and propose an endurance management scheme for it. The proposed endurance-aware compilation is capable of handling different trade-offs between write balance, latency, and area of the resulting PLiM implementations. Experimental evaluations on a set of benchmarks including large arithmetic and control functions show that the standard deviation of writes can be reduced by 86.65% on average compared to a naive compiler, while the average number of instructions and RRAM devices also decreases by 36.45% and 13.67%, respectively.

Memristive Stateful Logic for Edge Boolean Computers

“…There are two types of parallel computing: in-memory parallel computing [28,29,35,37,39,48,49,55,61,62,[97][98][99][100][101][102][103][104][105][106][107] and near-memory parallel computing utilizing an additional cache memory. [72,74,77,[108][109][110][111] For parallel computing, the operands must be aligned before the operation, making the data manipulation more important. In this section, we will discuss the parallel operation of stateful logic and the data manipulation strategy for complicated stateful logic computing.…”

ReTransformer

“…We base our choice of in-memory logic technology on the consideration of moving postprocessing closer to the processing subarrays and lowering the power consumption. Note that device endurance remains an open issue in contemporary in-memory logic designs that using emerging ReRAM devices [11,26]. Fortunately, the rapidly advancing fabrication and compilation [26] technologies offer a good promise to significantly enhance the reliability.…”

Architectures and automation for beyond-CMOS technologies

“…The method supports mapping to a wide variety of crossbar dimensions. has been done for Quantum-dot cellular automata in [127,128], and for ReRAM device-level endurance management in the context of in-memory computing [129], to the best of our knowledge, none of these works have considered the opportunity to exploit bit-level parallelism available in crossbar arrays. In this chapter, we extend in this direction by proposing a novel logic synthesis flow that optimizes the logic network to harness the inherent parallelism of the ReRAM crossbar arrays.…”