Static energy reduction by performance linked dynamic cache resizing

Chakraborty, Shounak; Kapoor, Hemangee K.

doi:10.1109/vlsi-soc.2016.7753549

Cited by 6 publications

(7 citation statements)

References 16 publications

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“…[31]. Chakraborty et al proposed working set size based cache resizing to reduce energy consumption [7]. However, none of the above approaches takes vulnerability into consideration.…”

Section: Dynamic Cache Reconfiguration and Partitioningmentioning

confidence: 99%

Cache Reconfiguration Using Machine Learning for Vulnerability-aware Energy Optimization

Ahmed

Huang

Mishra

2019

ACM Trans. Embed. Comput. Syst.

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Dynamic cache reconfiguration has been widely explored for energy optimization and performance improvement for single-core systems. Cache partitioning techniques are introduced for the shared cache in multicore systems to alleviate inter-core interference. While these techniques focus only on performance and energy, they ignore vulnerability due to soft errors. In this article, we present a static profiling based algorithm to enable vulnerability-aware energy-optimization for real-time multicore systems. Our approach can efficiently search the space of cache configurations and partitioning schemes for energy optimization while task deadlines and vulnerability constraints are satisfied. A machine learning technique has been employed to minimize the static profiling time without sacrificing the accuracy of results. Our experimental results demonstrate that our approach can achieve 19.2% average energy savings compared with the base configuration, while drastically reducing the vulnerability (49.3% on average) compared to state-of-the-art techniques. Furthermore, the machine learning technique enabled more than 10x speedup in static profiling time with a negligible prediction error of 3%.

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“…[31]. Chakraborty et al proposed working set size based cache resizing to reduce energy consumption [7]. However, none of the above approaches takes vulnerability into consideration.…”

Section: Dynamic Cache Reconfiguration and Partitioningmentioning

confidence: 99%

Cache Reconfiguration Using Machine Learning for Vulnerability-aware Energy Optimization

Ahmed

Huang

Mishra

2019

ACM Trans. Embed. Comput. Syst.

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“…In terms architecting LLC caches out STT-RAM, the most considered optimized solution for MCA by many designers is employing both SRAM and STT-RAM [94][95][96][97]. 11 EAI [102]. To ensure that power-gating techniques does not impose a significant threat on the performance, less likely used banks and powered-off and their requests forwarded to neighbouring requests [102].…”

Section: A Hybrid Architecturesmentioning

confidence: 99%

“…11 EAI [102]. To ensure that power-gating techniques does not impose a significant threat on the performance, less likely used banks and powered-off and their requests forwarded to neighbouring requests [102]. Other techniques on the hand, power-off cache ways instead of banks.…”

Section: A Hybrid Architecturesmentioning

confidence: 99%

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

Ofori-Attah¹,

Wang²,

Agyeman³

2018

EAI Endorsed Transactions on Industrial Networks and Intelligen

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Power consumption in Complementary Metal Oxide Semiconductor (CMOS) technology has escalated to a point that only a fractional part of many-core chips can be powered-on at a time. Fortunately, this fraction can be increased at the expense of performance through the dark-silicon solution. However, with manycore integration set to be heading towards its thousands, power consumption and temperature increases per time, meaning the number of active nodes must be reduced drastically. Therefore, optimized techniques are demanded for continuous advancement in technology. Existing efforts try to overcome this challenge by activating nodes from different parts of the chip at the expense of communication latency. Other efforts on the other hand employ run-time power management techniques to manage the power performance of the cores trading-off performance for power. We found out that, for a significant amount of power to saved and high temperature to be avoided, focus should be on reducing the power consumption of all the on-chip components. Especially, the memory hierarchy and the interconnect. Power consumption can be minimized by, reducing the size of high leakage power dissipating elements, turning-off idle resources and integrating power saving materials.

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“…Particularly, when there is a sudden overshoot in the workloads. Therefore, power-gating techniques should consider performance degradation when resizing the cache (cache banks and ways are powered-off) [36].…”

Section: Resizing Cache Sizementioning

confidence: 99%

“…Chakraborty et al [36] proposed a bank shutdown technique to reduce the power consumption in the LLCs. The banks that are less likely to be used are powered-off and their future requests redirected to neighbouring banks with average utilization.…”

Section: Resizing Cache Sizementioning

confidence: 99%

A Survey of Low Power Design Techniques for Last Level Caches

Ofori-Attah

Wang

Agyeman

2018

Applied Reconfigurable Computing. Architectures, Tools, and Applications

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The end of Dennard scaling has shifted the focus of performance enhancement in technology to power budgeting techniques, specifically in the nano-meter domain because, leakage power depletes the total chip budget. Therefore, to meet the power budget, the number of resources per die could be limited. With this emerging factor, power consumption of on-chip components is detrimental to the future of transistor scaling. Fortunately, earlier research has identified the Last Level Cache (LLC) as one of the major power consuming element. Consequently, there have been several efforts towards reducing power consumption in LLCs. This paper presents a survey of recent contribution towards reducing power consumption in the LLC.

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Static energy reduction by performance linked dynamic cache resizing

Cited by 6 publications

References 16 publications

Cache Reconfiguration Using Machine Learning for Vulnerability-aware Energy Optimization

Cache Reconfiguration Using Machine Learning for Vulnerability-aware Energy Optimization

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

A Survey of Low Power Design Techniques for Last Level Caches

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