Static hardware task placement on multi-context FPGA using hybrid genetic algorithm

Liang, Huixin; Sinha, Sharad; Warrier, Rakesh; Zhang, Wei

doi:10.1109/fpl.2015.7293954

Cited by 3 publications

(1 citation statement)

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“…In offline placement, all information about tasks' characteristics such as arrival time or dimensions are known before the program starts, and many time consuming computational methods like evolutionary algorithms are used to find an optimum answer. For example, a hybrid placement strategy based on genetic and greedy algorithms is proposed in [7] to efficiently place a set of tasks before system starts to work. On the other hand online algorithms decide with no information about incoming tasks in the future.…”

Section: Introductionmentioning

confidence: 99%

On-Line Reusing-Based Scheduling Algorithm for 2-Dimensional Tasks in Reconfigurable Hardware

2018

Trans. Mach. Intell.

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Reducing reconfiguration overhead is one of the main topics in increasing speed and performance of dynamically reconfigurable Field-Programmable Gate Arrays (FPGA). In this paper, an approach for reusing a repetitive hardware task in 2-dimensional hardware is proposed. At first, incoming tasks are divided into significant and non-significant tasks based on their features. Each group is placed in a specific partition of hardware and several methods such as replacement of significant tasks, using empty spaces in other partition or extending the partition border are applied to better use the resources. Conducted experiments show that in repetitive programs, the proposed method has %20.3 less makespan and decides more than 3 times faster than state-of-the-art algorithms in this field.

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Section: Introductionmentioning

confidence: 99%