Static‐noise margin analysis for a scaled‐down CMOS memory cell

Douseki, Takakuni; Mutoh, S.

doi:10.1002/ecjb.4420751111

Cited by 10 publications

(10 citation statements)

References 10 publications

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“…The cell stability of a memory array is often characterized using static-noise margin (SNM), where noiselike mismatches and disturbances are modeled as dc offsets [17]- [19]. When these dc offsets exceed the SNM of an SRAM cell, the cell performs a false switch, i.e., assume a wrong logic value.…”

Section: A Drowsy-cache Working Principlesmentioning

confidence: 99%

Fault Modeling and Detection for Drowsy SRAM Caches

Pei

Jone

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Due to the spatial-locality property of data caches and the temporal-locality property of instruction caches, significant leakage reduction can be achieved by switching a large number of cache lines into the low-power standby or drowsy mode. It has been shown that 80%-90% of the data cache lines can be maintained in drowsy state without affecting the performance by more than 0.6% (IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 2, pp. 167-184, Feb. 2004). However, with the introduction of the drowsy-cache design technique, new fault behaviors appear and more restrictive design rules must be applied to the chip fabrication process. In this paper, we simulate all possible spot defects (SDs) under normal mode and drowsy mode in different resistance regions using HSpice. Six new fault models appear with the introduction of drowsy mode for memory arrays. When we derive a march algorithm for the new fault models of this low-power cache, several simplification rules are utilized to reduce the test complexity. According to these simplification rules, each of these new faults has its equivalent counterpart existent in both data caches and instruction caches. As a result, we develop a march algorithm which can detect all SDs in either data caches or instruction caches. Since some faults occur only in drowsy mode, a built-in self-repair (BISR) scheme is developed. By utilizing BISR, the cache can still work even if some cache lines fail to work in drowsy mode.Index Terms-Built-in self-repair, drowsy cache, fault modeling, low-power design, march algorithm, memory testing.

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Section: A Drowsy-cache Working Principlesmentioning

confidence: 99%

Fault Modeling and Detection for Drowsy SRAM Caches

Pei

Jone

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Figure 4 (a) is called a butterfly plot and illustrates a read margin in a memory cell at n=0 (no Vth variations) and n=3. Figure 4 (b) shows a definition of a write margin [10]. The read and write margins worsen if Vth variation occurs, which raises Vmin.…”

Section: /√Lw (Au) Standard Deviation Of Vthmentioning

confidence: 99%

A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond

Morita¹,

Fujiwara²,

Noguchi³

et al. 2006

IEICE Transactions on Fundamentals of Electronics, Communicatio

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SummaryWe propose a voltage control scheme for 6T SRAM cells that makes a minimum operation voltage down to 0.3 V under DVS environment. A supply voltage to the memory cells and wordline drivers, bitline voltage, and body bias voltage of load pMOSFETs are controlled according to read and write operations, which secures operation margins even at a low operation voltage. A self-aligned timing control with a dummy wordline and its feedback is also introduced to guarantee stable operation in a wide range of the supply voltage. A measurement result of a 64-kb SRAM in a 90-nm process technology shows that a power reduction of 30% can be achieved at 100MHz. In a 65-nm 64-Mb SRAM, a 74% power saving is expected at 1/6 of the maximum operating frequency. The performance penalty by the proposed scheme is less than 1%, and area overhead is 5.6%.

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“…In the 6T cell, we have to pay attention to both read and write margins as illustrated in Fig. 3 [3]. The schematics in the figure signify the assignments of the local V th variations on the worst-case read and write conditions.…”

Section: Introductionmentioning

confidence: 99%

“…The read margin in the 6T cell correlates with a logical V th of an inverter (Nd2 and Pl2), and is inversely related to a minimum output voltage of the inverter latch (V RO in Fig. 3(a)) [3]. If the width of the access transistor (W a ) is increased, that is, if the β ratio is decreased, V RO becomes larger.…”

Section: Introductionmentioning

confidence: 99%

Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes

Morita

Fujiwara²,

Noguchi³

et al. 2007

IEICE Transactions on Electronics

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This paper shows that an 8T SRAM cell is superior to a 6T cell in terms of cell area in a future process. At a 65-nm node and later, the 6T cell comprised of the minimum-channel-length transistors cannot make the minimum area because of threshold-voltage variation. In contrast, the 8T cell can employ the optimized transistors and achieves the minimum area even if it is used as a single-port SRAM. In a 32-nm process, the 8T-cell area is smaller than the 6T cell by 14.6% at a supply voltage of 0.8 V. We also discuss the area and access time comparisons between the 6T-SRAM and 8T-SRAM macros.

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Static‐noise margin analysis for a scaled‐down CMOS memory cell

Cited by 10 publications

References 10 publications

Fault Modeling and Detection for Drowsy SRAM Caches

Fault Modeling and Detection for Drowsy SRAM Caches

A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond

Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes

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