Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes

Abstract

This paper shows that an 8T SRAM cell is superior to a 6T cell in terms of cell area in a future process. At a 65-nm node and later, the 6T cell comprised of the minimum-channel-length transistors cannot make the minimum area because of threshold-voltage variation. In contrast, the 8T cell can employ the optimized transistors and achieves the minimum area even if it is used as a single-port SRAM. In a 32-nm process, the 8T-cell area is smaller than the 6T cell by 14.6% at a supply voltage of 0.8 V. We also discuss the area and access time comparisons between the 6T-SRAM and 8T-SRAM macros.

An Ultra Low Power Space Application based Radiation-Hardened Low Voltage 4T SRAM Bitcell

“…Two additional access transistors serve to control the access to a storage cell during read and write operations.In addition to such sixtransistor (6T)SRAM, other kinds of SRAM chips use 4, 8, 10 (4T, 8T, 10T SRAM), or more transistors per bit. [4], [5], [6].Fourtransistor SRAM is quite common in stand-alone SRAM devices(as opposed to SRAM used for CPU caches), implemented in special processes with an extra layer of polysilicon, allowing for very high-resistance pull-up resistors [7].Four transistor SRAM provides advantages in density at the cost of manufacturing complexity.The resistors must have small dimensions and large values.This sometimes used to implement more than one(read and or write) port, which may be useful in certain types of video memory and register files implemented with multi-ported SRAM circuitry. Generally, the fewer transistors needed per cell, the smaller each cell can be.…”

Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme

“…1(b) by 10% at the 90-nm node, which is due to the separate read port. We have clarified that, in a single-V dd scheme, the area of the 8T cell can be smaller than that of the 6T cell even if the 8T cell is utilized as a single-port SRAM cell [3].…”