The threshold voltage (VT) drifts caused by Negative-Bias Temperature Instability (NBTI) and Positive-Bias Temperature Instability (PBTI) degrade stability, margin, and performance of nanoscale SRAM over the lifetime of usage. Moreover, most state-of-theart SRAMs employ replica timing control scheme to mitigate the effects of excessive leakage and variation, and NBTI/PBTI induced V T drifts can render the scheme ineffective or even useless. In this paper, we investigate impacts of NBTI and PBTI on SRAM Write operations based on PTM 32nm CMOS technology node poly-gate and high-k metal-gate models. We propose an NBTI/PBTI tolerant Write-replica timing control scheme to mitigate Write margin and performance degradation. By using multi-bank architecture and biasing the virtual supply line of inactive timing-critical circuits to GND to minimize the stress time and maximize the "Recovery" period, the NBTI/PBTI induced SRAM Write performance degradation can be reduced by around 32-48%.
In this paper, a micro-watt multi-port register file with wide operating voltage range for micro-power applications is presented. Multibank architecture for simultaneous access with collision detecting technique is proposed. The architecture has been analyzed under wide operating voltage range between 1V to 0.25V with varies process corner. Negative voltage write scheme ensures successful write in deep sub-threshold region. Also, an improved read buffer footer and controllable pre-charge in read scheme are designed. A 4W/4R 16KB register file is implemented in UMC 90nm CMOS technology. The simulation results show that the maximum active power of multi-port register file can achieve near 22.3-22.9uW at 485 KHz under 0.25V.Fig. 1: Proposed register file in VLIW DSP.
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