Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM

BTI and HCI first-order aging estimation for early use in standard cell technology mapping

“…The aging models have been calibrated to provide, in the worst case, a V th degradation of 50 mV for BTI and HCI. These maximum degradation levels represent similar values used by other works in the literature [5][6][7][8][9][10][11][12][13]16,17].…”

Impacts of NBTI/PBTI on performance of domino logic circuits with high-k metal-gate devices in nanoscale CMOS

“…We have accurately fit the above formulation with the V th drift values reported in [8] for PTM High-k 32-nm device model with a supply voltage of 0.9 V and a temperature of 125°C. The resulted values are shown in Fig.…”

“…Under dynamic operation conditions, the DC RD model is modified by a prefactor to account for the recovery mechanism (AC RD model). This prefactor is a function of the signal (stress) probability and is relatively independent of the signal frequency [8]. We have modeled the V th drift due to NBTI/PBTI based on an exponential behavior as proposed in [7] which is expressed by…”

A Review on aging aware Reliable Multiplier

“…However, for high-k/metal-gate nMOS transistors with significant charge trapping, the PBTI effect can no longer be ignored. In fact, it has been shown that the PBTI effect is more significant than the NBTI effect on 32-nm high-k/metal-gate processes [1]- [2]. Traditional circuits use critical path delay as the overall circuit clock cycle in order to perform effectively.…”