Static test compaction for scan-based designs to reduce test application time

Pomeranz, Irith; Reddy, S.M.

doi:10.1109/ats.1998.741614

Cited by 49 publications

(104 citation statements)

References 13 publications

Supporting

Mentioning

104

Contrasting

Order By: Relevance

“…Some of these use software procedures to obtain a sequence whose application to the circuit requires the lowest number possible of clock cycles. The hybrid scan/sequential technique [26], the method based on active-overlapping techniques [8], and the procedure for combining test subsequences [24], are some interesting examples. All of the above techniques require the use of specific software and use sequential test generation tools and/or sequential fault simulation.…”

Section: Background and Related Workmentioning

confidence: 99%

Reducing test application time, test data volume and test power through Virtual Chain Partition

Solana

2009

Integration

View full text Add to dashboard Cite

Section: Background and Related Workmentioning

confidence: 99%

Reducing test application time, test data volume and test power through Virtual Chain Partition

Solana

2009

Integration

View full text Add to dashboard Cite

“…The original test set in this case is the one obtained by static compaction [13]. Table 5 is organized as follows.…”

Section: Resultsmentioning

confidence: 99%

“…In Table 3, we show the following information for the test sets obtained by static compaction [13]. Under column original , we show the number of tests in T , the length of all the input sequences T i in T , and the number of bits required to store T .…”

Section: Resultsmentioning

confidence: 99%

“…The values of the state variables obtained under c i are assigned to the scan-in vector SI i ; and the primary input vector obtained under c i is included in a test sequence T i of length one. Starting from the test set obtained in this way, we apply the static compaction procedure of [13]. After static compaction, the number of tests is lower and the lengths of the sequences T i is higher (the lower number of tests reduces the number of scan operations and the test application time; the total length of all the primary input sequences is kept the same or it is reduced by compaction).…”

Section: Resultsmentioning

confidence: 99%

See 1 more Smart Citation

A partitioning and storage based built-in test pattern generation method for scan circuits

Pomeranz

Reddy

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conferen

Self Cite

View full text Add to dashboard Cite

We describe a built-in test pattern generation method for scan circuits. The method is based on partitioning and storage of test sets. Under this method, a precomputed test set is partitioned into several sets containing values of different primary inputs or state variables. The on-chip test set is obtained by implementing the Cartesian product of the various sets. The sets are reduced as much as possible before they are stored on-chip in order to reduce the storage requirements and the test application time.

show abstract

“…A number of schemes have been proposed for test data volume reduction of scan-based deterministic test by improving the effectiveness of test compaction [1,3,8,16] and compression schemes [2,5,9,11,12,13,18,19]. While both compaction and compression schemes aim at reducing test data volume, the way that they attack the problem of test data volume reduction differs.…”

Section: Previous Workmentioning

confidence: 99%

Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression

Bayraktaroglu

Orailoğlu

Proceedings. 21st VLSI Test Symposium, 2003.

View full text Add to dashboard Cite

A methodology for the determination of decompression hardware that guarantees complete fault coverage for a unified compaction/compression scheme is proposed. Test cube information is utilized for the determination of a near optimal decompression hardware. The proposed scheme attains simultaneously high compression levels and reduced pattern counts through a linear decompression hardware. Significant test volume and test application time reductionsare delivered through the scheme we propose while a highly cost effective hardware implementation is retained.

show abstract

Static test compaction for scan-based designs to reduce test application time

Cited by 49 publications

References 13 publications

Reducing test application time, test data volume and test power through Virtual Chain Partition

Reducing test application time, test data volume and test power through Virtual Chain Partition

A partitioning and storage based built-in test pattern generation method for scan circuits

Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression

Contact Info

Product

Resources

About