Static variable ordering in ZBDDs for path delay fault coverage calculation

Path Representation in Circuit Netlists Using Linear-Sized ZDDs with Optimal Variable Ordering

“…The BDD ordering techniques have been used in the vast majority of the works for ZDDs. The works in [21] and [24] attempt to incorporate concepts from BDD variable ordering to ZDDs, both specific to the problem they examine. None of these two methods provide an upper bound of the size of the obtained ZDD.…”

“…Specifically, [21] proposes a good variable order for frequent itemsets used in data mining with very good improvements over the previously used approaches, yet its applicability is limited to the problem considered. The approach of [24] is also specific to the examined problem of path delay fault coverage calculation for digital circuits. As this work also uses the PDF coverage problem to demonstrate the effectiveness of the proposed theory, we have included appropriate discussion and experimentation in Section 4.…”

“…Previous work on path representation in digital circuits has been developed in relation to the Path Delay Fault (PDF) model [42], where a fault is a logical circuit path modeled as a delayed transition across a structural path. Several related problems have been inves-tigated, for the PDF model including PDF simulation (or grading) [2,17,24,28,36,41].…”

“…While the latter method can, in the worst case, result in an exponentially large structure, in practice ZDDs have been shown to cope well when representing paths. A preliminary experimental study investigating the size of ZDDs when representing paths under different ZDD variable orderings was performed in [24]. Yet, none of the existing works addresses the complexity and optimality of the variable ordering.…”

“…We have chosen to compare with[25] instead of the same authors' previous work in[24] which proposes a specific variable ordering, as the results in[25] demonstrate small improvement over[24].…”