Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays

Essen, Brian Van; Wood, Aaron; Carroll, Allan; Friedman, Stephen; Panda, Robin; Ylvisaker, Benjamin; Ebeling, Carl; Hauck, Scott

doi:10.1109/fpl.2009.5272293

Cited by 16 publications

(10 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Instead, connectivity can be tailored to the set of segments or an application domain. Different interconnection topologies for meshes are evaluated in References [63,93,98]. Likewise, quantitative analyses can determine connectivity requirements between rows of a row-based array [68,85,103].…”

Section: Fu Interconnectionsmentioning

confidence: 99%

Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey

2020

View full text Add to dashboard Cite

The breakdown of Dennard scaling has resulted in a decade-long stall of the maximum operating clock frequencies of processors. To mitigate this issue, computing shifted to multi-core devices. This introduced the need for programming flows and tools that facilitate the expression of workload parallelism at high abstraction levels. However, not all workloads are easily parallelizable, and the minor improvements to processor cores have not significantly increased single-threaded performance. Simultaneously, Instruction Level Parallelism in applications is considerably underexplored. This article reviews notable approaches that focus on exploiting this potential parallelism via automatic generation of specialized hardware from binary code. Although research on this topic spans over more than 20 years, automatic acceleration of software via translation to hardware has gained new importance with the recent trend toward reconfigurable heterogeneous platforms. We characterize this kind of binary acceleration approach and the accelerator architectures on which it relies. We summarize notable state-of-the-art approaches individually and present a taxonomy and comparison. Performance gains from 2.6× to 5.6× are reported, mostly considering bare-metal embedded applications, along with power consumption reductions between 1.3× and 3.9×. We believe the methodologies and results achievable by automatic hardware generation approaches are promising in the context of emergent reconfigurable devices.

show abstract

Section: Fu Interconnectionsmentioning

confidence: 99%

Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey

2020

View full text Add to dashboard Cite

show abstract

“…These kinds of algorithms could be combined with trivial failure handling, but we chose not to perform these comparisons because they would not shed light on the central issue of the importance of handling failures intelligently. We performed our experiments in the context of a research architecture and toolflow developed at the University of Washington, called Mosaic [9,20]. Mosaic architectures are FPGA-like, but with coarse-grained interconnect and ALUs.…”

Section: Neighborhood Graphmentioning

confidence: 99%

Probabilistic auto-tuning for architectures with complex constraints

Ylvisaker

Hauck

2011

Proceedings of the 1st International Workshop on Adaptive Self-Tuning Computing Systems for the Exaflop Era

Self Cite

View full text Add to dashboard Cite

It is hard to optimize applications for coprocessor accelerator architectures, like FPGAs and GPUs, because application parameters must be tuned carefully to the size of the target architecture. Moreover, some combinations of parameters simply do not work, because they lead to overuse of a constrained resource. Applying auto-tuning-the use of search algorithms and empirical feedback to optimize programs-is an attractive solution, but tuning in the presence of unpredictable failures is not addressed well by existing auto-tuning methods.This paper describes a new auto-tuning method that is based on probabilistic predictions of multiple program features (run time, memory consumption, etc.). During configuration selection, these predictions are combined to balance the preference for trying configurations that are likely to be high quality against the preference for trying configurations that are likely to satisfy all constraints. In our experiments, our new auto-tuning method performed substantially better than the simpler approach of treating all failed configurations as if they succeed with a "very low" quality. In many cases, the simpler strategy required more than twice as many trials to reach the same quality level in our experiments.

show abstract

“…Therefore, CGRAs have been a subject of intensive research since the last decade [2,5,6]. A number of research efforts have attempted to integrate time-multiplexing [7], runtime parallelism [8][9][10][11], and power management in CGRAs [10,11]. While these approaches do reduce energy and area overheads, they http significantly enhance the configuration memory requirements.…”

Section: Introductionmentioning

confidence: 99%