Statistical Analysis for Pattern-Dependent Simultaneous Switching Outputs (SSO) of Parallel Single-Ended Buffers

Kim, Jingook

doi:10.1109/tcsi.2016.2611009

Cited by 26 publications

(11 citation statements)

References 25 publications

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“…Previous works [ 20 , 21 ] proposed the statistical eye-diagram estimation method considering power/ground noise generated by SSO for the first time. However, it does not consider steady states affected by SSO.…”

Section: Verification Of the Proposed Statistical Methodsmentioning

confidence: 99%

“… Comparison between statistical eye-diagrams estimated based on previous methods [ 20 , 21 ] ( a ) and estimated based on the proposed method. ( b ) Total of 16 buffers are in operation, generating SSO effects at the data rate of 1 Gb/s.…”

Section: Figurementioning

confidence: 99%

“…Double edge response (DER) and multiple edge response (MER) methods are capable of capturing the non-linearity impacts, but they are difficult to reflect the impacts of SSO noise [ 16 , 17 , 18 , 19 ]. In previous works [ 20 , 21 ], the statistical eye-diagram estimation method, which is capable of considering SSO impact, is proposed for the first time. However, the steady-states response affected by the SSO are not considered.…”

Section: Introductionmentioning

confidence: 99%

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A Statistical Approach for Signal and Power Integrity Co-Design in High-Speed Interconnects Considering Non-Linear Power/Ground Noise and Bit-Patterns

Kim

2023

Micromachines

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In this article, a novel statistical approach is proposed and applied to co-design signal and power integrity (SI/PI) in high-speed interconnects considering the non-linear power/ground noise generated by parallel buffers and bit-patterns. With increased data rates and decreased operating voltages, the allowed noise margin in high-speed interconnects is continuously reduced, and this trend requires SI/PI co-design. Specifically, non-linear power/ground noise associated with simultaneous switching circuits sharing a power delivery network (PDN) and bit-patterns must be carefully considered during the interconnects’ design and analysis phase. In many cases, conventional electromagnetic (EM) and transient circuit simulators require heavy computational resources or even fail to deliver an accurate result. The proposed statistical method estimates the statistical eye-diagram in the high-speed interconnect considering power/ground noise and bit-patterns such as data bus inversion (DBI) coding. The accuracy and computational efficiency of the proposed method are validated by comparing the result with HSPICE transient simulation result. The proposed method is also compared with conventional statistical methods, such as peak distortion analysis (PDA) and statistical channel simulation in the transient simulator. Lastly, the proposed method is applied to the SI/PI co-design and co-analysis in the high bandwidth memory (HBM) interposer channel. Impacts of decoupling capacitors on hierarchical PDN impedance, statistical eye-diagram of the HBM channel, and bit error rate (BER) Bathtub curves are summarized. Finally, the BER eye-diagram is derived from the estimated statistical eye-diagram for timing and voltage analysis. The impacts of hierarchical PDN design and bit-patterns on SI/PI are discussed.

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Section: Verification Of the Proposed Statistical Methodsmentioning

confidence: 99%

Section: Figurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Statistical Approach for Signal and Power Integrity Co-Design in High-Speed Interconnects Considering Non-Linear Power/Ground Noise and Bit-Patterns

Kim

2023

Micromachines

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“…Power supplies and an external single-ended clock are transmitted to a chip by bonding wires, which connect a chip pad and a printed circuit board (PCB) pad. However, the high-speed signals incur more notable ground bounce due to bonding wire inductors and pad capacitors [24,25,26]. Furthermore, the ground bounce is equivalent to a common-mode noise and added to all signals shared the same reference ground [27,28,29].…”

Section: Model Of the Bonding Wirementioning

confidence: 99%

A quadrature LO-generator using an external single-ended clock receiver for dual-band WLAN applications

Tian

Huang

2021

IEICE Electron. Express

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A low phase noise quadrature LO-generator for dual-band wireless local area network (WLAN) applications is presented. The quadrature LO-generator is composed of a clock receiver, a CML divider, and two quadrature dividers for the dual-band, respectively. A clock receiver converts the single-ended clock to a differential signal. Then a quadrature divider with a 25% duty cycle generates four quadrature signals for mixers. The split-grounded architecture and multiply ground pads decrease the inductive component of ground impedance as well as the ground bounce of the single-ended input. The phase noise is −143dBc/Hz and −149dBc/Hz at 1MHz offset in the 2.4-GHz and 5-GHz bands, respectively.

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“…The timing analysis at the output of a delay-line or a tapered buffer in the presence of PSN can be performed using various methods [4], [6], [9]- [11], [14], [15]. In this paper, a simplified semi-analytical approach is developed for the analysis of TIE (as well as the jitter) at the output of a delayline or tapered buffer that are designed using CMOS inverters.…”

Section: Problem Formulationmentioning

confidence: 99%

A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers

et al. 2019

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This paper presents an efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources. Generalised semi-analytical relations between noise and PSIJ are developed using Thomas algorithm. The proposed analysis can be used for both cases of same size of inverters as well as tapered buffers, and also for considering the effect of on-chip and off-chip interconnects. The validity and the efficiency of the proposed modeling is demonstrated for various applications of chain of inverters such as buffers in clock distribution, delay locked loops and I/Os, etc. INDEX TERMS CMOS inverter, chain of inverters, clock-network, delay-line, I/O, jitter, power supply noise, power supply induced jitter, time interval error, tapered buffer. APPENDIX C FORMULATION OF TRI-DIAGONAL MATRIX FOR EXAMPLE-3

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Statistical Analysis for Pattern-Dependent Simultaneous Switching Outputs (SSO) of Parallel Single-Ended Buffers

Cited by 26 publications

References 25 publications

A Statistical Approach for Signal and Power Integrity Co-Design in High-Speed Interconnects Considering Non-Linear Power/Ground Noise and Bit-Patterns

A Statistical Approach for Signal and Power Integrity Co-Design in High-Speed Interconnects Considering Non-Linear Power/Ground Noise and Bit-Patterns

A quadrature LO-generator using an external single-ended clock receiver for dual-band WLAN applications

A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers

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