Statistical Analysis of Metal Gate Workfunction Variability, Process Variation, and Random Dopant Fluctuation in Nano-CMOS Circuits

Hwang, C. S.; Li, Tien-Yeh; Han, Ming-Hung; Lee, Kuo-Fu; Cheng, Hui-Wen; Li, Yiming

doi:10.1109/sispad.2009.5290239

Cited by 9 publications

(4 citation statements)

References 16 publications

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“…When W is varied we may either face volume inversion or may not, depending upon the channel doping levels. When the channel doping is 1x10 16 /cm 3 volume inversion is not seen [14]. Therefore, the increase in W increases current and thereby g m and f t .…”

Section: Variation In Fin Widthmentioning

confidence: 99%

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Statistical Modelling of ft to Process Parameters in 30 NM Gate Length Finfets

Lakshmi¹,

Srinivasan²

2010

VLSICS

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Section: Variation In Fin Widthmentioning

confidence: 99%

“…High frequency characteristics are less sensitive to work function variation [16]. Therefore, f t is expected to be indifferent to gate electrode work function.…”

Section: Variation In Work Functionmentioning

confidence: 99%

Statistical Modelling of ft to Process Parameters in 30 NM Gate Length Finfets

Lakshmi¹,

Srinivasan²

2010

VLSICS

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“…The dimension of effective devices has shrunk to a sub-22 nanometer scale, and due to this, we are facing even more serious characteristic variability problems [1,2,3,4,5,6,7]. High-κ/metal gate (HKMG) technology has been recognized as a solution to solve intrinsic fluctuation, but the crystal orientation of nanosized metal grain is uncontrollable during the growth step under high temperatures [8,9].…”

Section: Introductionmentioning

confidence: 99%

Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits

Chen

Chuang

et al. 2019

Materials

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In this study, we investigate direct current (DC)/alternating current (AC) characteristic variability induced by work function fluctuation (WKF) with respect to different nanosized metal grains and the variation of aspect ratios (ARs) of channel cross-sections on a 10 nm gate gate-all-around (GAA) nanowire (NW) metal–oxide–semiconductor field-effect transistor (MOSFET) device. The associated timing and power fluctuations of the GAA NW complementary metal–oxide–semiconductor (CMOS) circuits are further estimated and analyzed simultaneously. The experimentally validated device and circuit simulation running on a parallel computing system are intensively performed while considering the effects of WKF and various ARs to access the device’s nominal and fluctuated characteristics. To provide the best accuracy of simulation, we herein calibrate the simulation results and experimental data by adjusting the fitting parameters of the mobility model. Transfer characteristics, dynamic timing, and power consumption of the tested circuit are calculated using a mixed device–circuit simulation technique. The timing fluctuation mainly follows the trend of the variation of threshold voltage. The fluctuation terms of power consumption comprising static, short-circuit, and dynamic powers are governed by the trend that the larger the grain size, the larger the fluctuation.

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“…Considering that the operation of nanodevices (currently the logic and memory technology is advancing towards the 10-22 nm node) is governed by a few charge carriers (electrons/ holes) and/or atoms/ions [5], the current/voltage noise can be a significant factor that can provide in-depth insight into the underlying mechanism. This suggests that noise in the time and frequency domains can serve as a very good diagnostic tool [6].…”

Section: Introductionmentioning

confidence: 99%