Statistical Evaluation of Electromigration Reliability at Chip Level

Li, Baozhen; McLaughlin, P.; Bickford, Jeanne Paulette; Habitz, Peter; Netrabile, Dileep; Sullivan, Timothy D.

doi:10.1109/tdmr.2010.2093526

Cited by 25 publications

(10 citation statements)

References 11 publications

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“…A typical EM failure criterion for a wire is a resistance increase of 10%. To translate wire failure to system failure, the weakest link model [9,20] has been widely used for EM analysis. This is based on the idea that a chip fails on the first EM event, i.e., the chiplevel EM failure probability corresponds to the case where no wire experiences EM.…”

Section: Analysis Of Interconnect Systems 41 the Weakest Link Modelmentioning

confidence: 99%

Electromigration-Aware Interconnect Design

Sapatnekar

2019

Proceedings of the 2019 International Symposium on Physical Design

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Electromigration (EM) is seen as a growing problem in recent and upcoming technology nodes, and affects a wider variety of wires (e.g., power grid, clock/signal nets), circuits (e.g., digital, analog, mixed-signal), and systems (e.g., mobile, server, automotive), touching lower levels of metal than before. Moreover, unlike traditional EM checks that were performed on each wire individually, EM checks must evolve to consider the system-level impact of wire failure. This requires a change in how interconnect design incorporates this effect. This paper overviews the root causes of EM, its impact on high-performance designs, and techniques for analyzing, working around, and alleviating the effects of EM. CCS CONCEPTS • General and reference → Reliability; • Hardware → Metallic interconnect; Very large scale integration design; Electronic design automation; Physical design (EDA); Aging of circuits and systems; Analog and mixed-signal circuits.

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Section: Analysis Of Interconnect Systems 41 the Weakest Link Modelmentioning

confidence: 99%

Electromigration-Aware Interconnect Design

Sapatnekar

2019

Proceedings of the 2019 International Symposium on Physical Design

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“…The most prominent degradation modes are reported to be bias temperature instability (BTI) [2], hot carrier degradation (HCD) [3], time dependent dielectric breakdown (TDDB) [4] and electro migration (EM) [5]. A designer needs to address these issues within his design flow in order to design for a specific reliability requirement.…”

Section: Introductionmentioning

confidence: 99%

An aging-aware transistor sizing tool regarding BTI and HCD degradation modes

Hellwege

Heidmann

Erstling

et al. 2015

2015 22nd International Conference Mixed Design of Integrated Circuits &Amp; Systems (MIXDES)

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In this paper we present a tool based approach for an aging-aware design method. Extending the gm /I D sizing method by operating point-dependent degradation caused by BTI and HCD enables an innovative design flow. This design flow considers performance characteristics for a fresh circuit and also those of a degraded circuit at design time. Once the degradation from a single transistor is computed, the GMID-Tool does not need any further SPICE or aging simulation. The impact of the change in design methodology is shown for a typical differential amplifier structure.

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“…Multiple publications have emphasized the increased complexity of making an accurate chip-level calculation of the percent fail due to EM [1][2][3][4][5][6]. Optimized EM validation targets are necessary for the design of interconnects to ensure the reliability of the final product while minimizing costs in schedule, resources, or die area due to overdesign.…”

Section: Introductionmentioning

confidence: 99%

Practical implications of chip-level statistical electromigration

Schmitz

2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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The accurate setting of electromigration (EM) design guidelines early is necessary to achieve chip-level fail goals. The issue is even more critical with the recognition of the percentage fail as a stochastic issue based on the individual EM elements. The challenge is the degree to fix those elements prior to the knowledge of chip-level fail rate. This paper will demonstrate a test case and approaches to early design guidelines which have shown success at meeting chip-level EM fail goals

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Statistical Evaluation of Electromigration Reliability at Chip Level

Cited by 25 publications

References 11 publications

Electromigration-Aware Interconnect Design

Electromigration-Aware Interconnect Design

An aging-aware transistor sizing tool regarding BTI and HCD degradation modes

Practical implications of chip-level statistical electromigration

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