Statistical Investigation of Anomalous Fast Erase Dynamics in Charge Trapping NAND Flash

Abstract

In NAND Flash non-volatile memories the erase\ud operation drives the memory cells threshold voltage toward\ud negative values, barely representing a concern for Multi-Level\ud architectures. However, during the analysis of the erase dynamics\ud in Charge Trapping (CT) memory arrays using an Incremental\ud Step Pulse Erase algorithm, it has been found that a small\ud population of memory cells ( 2%) may randomly exhibit\ud anomalous fast erase dynamics which causes threshold voltage\ud fluctuations during cycling operations. The purpose of this letter\ud is to provide a statistical characterization of this phenomenon in\ud CT-NAND Flash arrays, thus helping the comprehension of its\ud underlying physical mechanisms

Quality-of-Service Implications of Enhanced Program Algorithms for Charge-Trapping NAND in Future Solid-State Drives

“…5b), with a maximum programming time of 6.97 ms for L3 distribution. These values have been chosen to minimize the disturbs and other unwanted phenomenon due to the soft-erase operation applied on all the cells within a common block [21].…”