Statistical lifetime reliability optimization considering joint effect of process variation and aging

Song, Junqiang; Han, Yinhe; Li, Huawei; Li, Xiaowei

doi:10.1016/j.vlsi.2011.03.004

Cited by 16 publications

(12 citation statements)

References 19 publications

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“…This problem is referred to as threshold voltage variation due to random dopant fluctuation (RDF), and it is considered a major problem in current technologies and expected to be worse in future technologies [18,21,22]. Since in smaller technologies, the total number of dopants is expected to be lower; thus, the problem is likely to be worse [11,20].…”

Section: Motivationmentioning

confidence: 99%

Reducing random-dopant fluctuation impact using footer transistors in many-core systems

Majzoub

2015

Integration

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Section: Motivationmentioning

confidence: 99%

Reducing random-dopant fluctuation impact using footer transistors in many-core systems

Majzoub

2015

Integration

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“…However, considering the interdependencies between BTI and PV [13], [14], such separate analysis leads to inaccurate and unrealistic results. Recently, some papers have addressed the combined impacts of process variability and NBTI or BTI at different levels of abstraction such as device-level [9], gatelevel [15]- [17], and architecture-level [18]- [20]. Siddiqua et al,in [21] explored both NBTI and PV in an SRAM cell.…”

Section: Introductionmentioning

confidence: 99%

“…Then, the model presents a PDF for the gate delay at a given year of stress time. A statistical circuit optimization flow introduced in [15] which improve combinational circuit lifetime reliability in the presence of the joint effect of PV and NBTI. Han et.al [22] proposed a stochastic model of the Vth value variation and the gate aging delay time which considers the effects of the PV on NBTI.…”

Section: Introductionmentioning

confidence: 99%

“…Based on transistor-level SPICE simulations, the delay degradation of each library cell is characterized under a set of variability and aging factors. It is notable that PV-and aging analysis methods suffer from limitations: some of the previous works only consider NBTI effect (and neglect PBTI) [14], [15], [21]- [25] or some others just focused on one challenge (either PV or aging effect) [8]- [11] leading to inaccurate analysis results. Moreover, most of the other works, which consider both PV and aging effects, use the old reactiondiffusion theory to consider NBTI and PBTI effects on circuits [7] [16].…”

Section: Introductionmentioning

confidence: 99%

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Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment

et al. 2021

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In nano-scale CMOS technology, circuit reliability is a growing concern for complicated digital circuits due to manufacturing process variation and aging effects. In this paper, a statistical circuit optimization framework is presented to analyze and improve the lifetime reliability of digital circuits in the presence of process variation and aging degradation. The proposed framework takes advantage of a process variation-and aging-aware gate-level delay degradation model to characterize and evaluate the lifetime reliability of combinational circuits. A metric called Guardband-Aware Reliability (abbreviated as GAR) is proposed for a fair evaluation of the lifetime reliability of combinational circuits considering a guardband and timing yield specified by the designer. Then, using a criticality metric, a set of statistically critical gates is selected for being optimized in the optimization framework. As the improvement procedure, the dualthreshold voltage assignment technique is applied to the identified critical gates to enable the manufactured chip to improve the lifetime reliability in terms of low timing yield loss. Experimental results on ISCAS'85 and ISCAS'89 benchmark circuits show that our proposed framework increases the circuit reliability up to 9.93% for a 6-year lifetime imposing less than 6.9% timing yield loss.

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“…Time-dependent reliability such as Bias Temperature Instability (BTI), significantly degrades the performance of a circuit during its operation course. Negative Bias Temperature Instability (NBTI) is one of the most critical issues for reliability of PMOS transistors [1][2][3][4][5][6][7][8]. In addition, the continued scaling reduction of CMOS technology to less than 45nm, introducing the High-K Metal Gate technology [9][10][11] and its dependence on charge trapping place the Positive Bias Temperature Instability (PBTI) effect as one of the biggest concerns in NMOS transistor reliability [11][12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

Adaptive Technique for Overcoming Performance Degradation Due to Aging on 6T SRAM Cells

Faraji

Naji

2014

IEEE Trans. Device Mater. Relib.

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The threshold voltage drifts induced by Positive Bias Temperature Instability (PBTI) and Negative Bias Temperature Instability (NBTI) weaken NMOS and PMOS, respectively. These long-term aging threshold voltage drifts degrade SRAM cell stability, margin and performance. This paper presents a low area overhead Adaptive Body Bias (ABB) circuit that compensates BTI aging effects and also improves performance of an aged SRAM cell. The proposed circuit uses a control circuit and word line voltage to control the voltage applied to the body of 6T SRAM cell's transistors such that the BTI effect dependency of threshold voltage is reduced. In the worst case, the proposed ABB reduces the HOLD SNM degradation by 6.85%, READ SNM degradation by 12.24%, WRITE margin degradation by 2.16%, READ delay by 28.68% and WRITE delay by 32.61% compared to the conventional SRAM cell at 10 8 seconds aging time.

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Statistical lifetime reliability optimization considering joint effect of process variation and aging

Cited by 16 publications

References 19 publications

Reducing random-dopant fluctuation impact using footer transistors in many-core systems

Reducing random-dopant fluctuation impact using footer transistors in many-core systems

Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment

Adaptive Technique for Overcoming Performance Degradation Due to Aging on 6T SRAM Cells

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