Statistical metrology—measurement and modeling of variation for advanced process development and design rule generation

Boning, Duane S.; Chung, J.E.

doi:10.1063/1.56906

Cited by 15 publications

(4 citation statements)

References 17 publications

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“…Generally they manifest themselves in both temporal and spatial manner. According to the geometrical scales of their occurrence, the variations are classified at four different levels [1]: lot-to-lot, wafer-to-wafer (within-lot), die-to-die (within-wafer) and within-die. Since our main interest is to determine the effects of variations on circuit timing performance, in this work we focus on the true geometrical variations.…”

Section: Characterization Of Interconnect Variationsmentioning

confidence: 99%

Impact of interconnect variations on the clock skew of a gigahertz microprocessor

Liu

Nassif

Pileggi

et al. 2000

Proceedings of the 37th Conference on Design Automation - DAC '00

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Due to the large die sizes and tight relative clock skew margins, the impact of interconnect manufacturing variations on the clock skew in today's gigahertz microprocessors can no longer be ignored. Unlike manufacturing variations in the devices, the impact of the interconnect manufacturing variations on IC timing performance cannot be captured by worst/best case corner point methods. Thus it is difficult to estimate the clock skew variability due to interconnect variations. In this paper we analyze the timing impact of several key statistically independent interconnect variations in a context-dependent manner by applying a previously reported interconnect variational order-reduction technique. The results show that the interconnect variations can cause up to 25% clock skew variability in a modern microprocessor design.

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Section: Characterization Of Interconnect Variationsmentioning

confidence: 99%

Impact of interconnect variations on the clock skew of a gigahertz microprocessor

Liu

Nassif

Pileggi

et al. 2000

Proceedings of the 37th Conference on Design Automation - DAC '00

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“…Variations could exist on the same wafer or different wafers or may be on different lots. Generally, lot-to-lot and wafer-to-wafer variations are more random in nature [6]. Intra-die variation is defined as the variations that occur within the same die or chip.…”

Section: Inter-die and Intra-die Variationmentioning

confidence: 99%

Automating Variation and Repeater Analysis in Physical Design of Integrated Circuits

Mahalik¹

2000

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Rapid advancement and innovation in semiconductor research have continuously helped in designing efficient and complex integrated circuits in miniature size. As the device technology, is aggressively scaling to improve the device performance, the issues related to device interconnects, power, and reliability have become a major concern for the designers. These challenges make the design and validation of ASIC extremely complicated. The primary idea of this work is to develop automation tools, to be used in the physical design flows to improve the efficiency of the design flow. The first tool named as variation analysis tool automates the on-chip variation modeling used in the post-layout timing closure phase in the physical design flows. The proposed variation analysis tool models three types of variations such as on-chip variation (OCV), advanced on-chip variation (AOCV) and parametric on-chip variation (POCV). The results of the proposed tool have compared with the Synopsys PrimeTime™ results, and the results show average around 98% accuracy compared to the PrimeTime™. The second tool is for automating repeater analysis in the physical design flows. The repeater automation tool can be used to automate the repeater or buffer insertion process, while technology process is changed from one to another. The tool can calculate the best possible repeater distance for any given metal layer and also, the number of repeaters, combinational or sequential for the user given distance and frequency. The accuracy of this script is compared with the repeater insertion based on the synthesis tools and also, the SPICE simulation. First and foremost, I would like to take this opportunity to thank all of my committee members especially Dr. Ataur R. Patwary. This work would not have been possible without his constant guidance, motivation, and support. He has been an excellent source of inspiration and ideas. He has continuously provided me with confidence and having faith in me. His dedication and hard work towards his students inspires me a lot. I am grateful to Dr. Ataur for dedicating his precious time to me and regularly allowing me to meet him after work-hours, providing advice and feedback on research work. I would like to extend my gratitude to Professor Xiaoyu Song, my thesis committee chair, for his support and help during the period of my thesis work. He had continuously helped and motivated me to continue doing good work while I was struggling. I would also like to thank Professor John M. Acken for serving on my thesis Defense Examination Committee and providing valuable inputs on thesis draft. He has always dedicated his time to review and provide feedback on the thesis paper carefully. I would also like to thank Dr. Douglas Hall for delivering his constant support and motivation to complete this work. He has always helped me in completing all the formal process required to complete this thesis and also provided valuable advice regarding my future goals. This work would not have been possible without the constant suppor...

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“…Such variations come from process variations such as Le and Vt [2,3,4] as well as supply voltage and temperature variations. Process variations cause timing uncertainty.…”

Section: Introductionmentioning

confidence: 99%

Analyzing statistical timing behavior of coupled interconnects using quadratic delay change characteristics

Chen

Hajjar²

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.

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Statistical metrology—measurement and modeling of variation for advanced process development and design rule generation

Cited by 15 publications

References 17 publications

Impact of interconnect variations on the clock skew of a gigahertz microprocessor

Impact of interconnect variations on the clock skew of a gigahertz microprocessor

Automating Variation and Repeater Analysis in Physical Design of Integrated Circuits

Analyzing statistical timing behavior of coupled interconnects using quadratic delay change characteristics

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