Statistical Modeling of Leakage Currents Through SiO&lt;inf&gt;2&lt;/inf&gt;/High-&amp;#x03BA; Dielectrics Stacks for Non-Volatile Memory Applications

Padovani, Andrea; Larcher, Luca; Verma, S.; Pavan, Paolo; Majhi, P.; Kapur, Pawan; Parat, Krishna; Bersuker, G.; Saraswat, Krishna C.

doi:10.1109/relphy.2008.4558955

Cited by 19 publications

(12 citation statements)

References 25 publications

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“…[19][20][21]. The most recent model that is best comparable to the one presented here is the statistical model reported by Vandelli et al 22 and Padovani 23,24 for technologically promising SiO 2 /HfO 2 structures. Aside from the different materials they investigate, their approach differs from ours, as they implemented interaction cross sections to derive transport rates instead of implementing and using the rates directly for the kinetic Monte Carlo algorithm here, cf.…”

Section: Methods -Kmc-model Of Al/alo X /Ausupporting

confidence: 77%

Kinetic Monte Carlo of transport processes in Al/AlOx/Au-layers: Impact of defects

et al. 2016

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Ultrathin films of alumina were investigated by a compact kMC-model. Experimental jV-curves from Al/AlOx/Au-junctions with plasma- and thermal-grown AlOx were fitted by simulated ones. We found dominant defects at 2.3-2.5 eV below CBM for AlOx with an effective mass mox∗=0.35 m0 and a barrier EB,Al/AlOx≈2.8 eV in agreement with literature. The parameterization is extended to varying defect levels, defect densities, injection barriers, effective masses and the thickness of AlOx. Thus, dominant charge transport processes and implications on the relevance of defects are derived and AlOx parameters are specified which are detrimental for the operation of devices.

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Section: Methods -Kmc-model Of Al/alo X /Ausupporting

confidence: 77%

Kinetic Monte Carlo of transport processes in Al/AlOx/Au-layers: Impact of defects

et al. 2016

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“…In practice, its theoretical advantages, i.e. the strong voltage dependence of the tunneling current, are mitigated when the high defect density of high-K materials is taken into account [24][25][26]. In fact, the Trap-Assisted Tunneling (TAT) contribution enhances significantly the leakage current at low fields, strongly reducing its voltage dependence and increasing its statistical variations.…”

Section: H Igh-k Band-gap Engineered Barriersmentioning

confidence: 99%

Fundamental reliability issues of advanced charge-trapping Flash memory devices

Larcher

Padovani

2010

2010 17th IEEE International Conference on Electronics, Circuits and Systems

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The basic reliability issues of Charge Trapping (CT) Flash memory devices will be discussed from a physical perspective, highlighting the reliability implications of process and technology innovations introduced to sustain the uninterrupted device scaling down. We will focus on the reliability issues related to the charge localization inside the trapping layer and the high-K band-gap engineered stacks introduced to implement both tunnel and blocking dielectrics.We will describe the physical mechanisms responsible of reliability degradation (data retention, array disturbs, endurance), discussing briefly the issues related to ultra-scaled and vertically stacked 3D Flash memory devices.

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“…The statistical modeling of leakage, which includes trap-totrap transition, was described in a number of papers [6][7][8][9]. The statistical distribution of SILC via SiO 2 with multi-trap tunneling taken into account was studied in papers [6,7].…”

Section: Introductionmentioning

confidence: 99%

“…The statistical distribution of SILC via SiO 2 with multi-trap tunneling taken into account was studied in papers [6,7]. The SILC in IPD stacks with high trap concentration were also modeled in [8,9]. Although SILC studies are very useful to compare the quality of one oxide with another, it is hard to estimate the number of bad bits in flash memory cell array using only SILC methodology.…”

Section: Introductionmentioning

confidence: 99%

Statistical retention modeling in floating-gate cell: ONO scaling

Serov

Shin

Kim

et al. 2009

2009 IEEE International Reliability Physics Symposium

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The simulation study of the ONO gate stack scaling, which includes the Monte-Carlo statistical analysis of timedependent Vth distribution and SILC is performed. Leakage through both tunneling and blocking oxide is taken into account including multi-trap tunneling paths. Exact 50nm floating-gate cell structure is used instead of simple 1D stack for modeling and comparison with experimental data. Analysis of the influence of trap parameters on scaling trends is given.

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Statistical Modeling of Leakage Currents Through SiO<inf>2</inf>/High-κ Dielectrics Stacks for Non-Volatile Memory Applications

Cited by 19 publications

References 25 publications

Kinetic Monte Carlo of transport processes in Al/AlOx/Au-layers: Impact of defects

Kinetic Monte Carlo of transport processes in Al/AlOx/Au-layers: Impact of defects

Fundamental reliability issues of advanced charge-trapping Flash memory devices

Statistical retention modeling in floating-gate cell: ONO scaling

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