Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies

Datta, Animesh; Bhunia, Swarup; Mukhopadhyay, Saibal; Banerjee, Nilanjan; Roy, Kaushik

doi:10.1109/date.2005.278

Cited by 17 publications

(12 citation statements)

References 9 publications

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“…For instance, a recent study on the effects of process variations on microprocessors has shown that the L1 cache has almost 60% chances of containing the critical path [10]. Another study also reports that process variations can have an uneven impact on the timing of different pipeline stages of a sequential circuit [1].…”

Section: Impact Of Process Variations On Timingmentioning

confidence: 99%

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Automated design of self-adjusting pipelines

Long

Memik

2008

Proceedings of the 45th Annual Design Automation Conference

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We propose a self-adjusting pipeline structure to enhance chip performance and robustness considering the effects of process variations. We achieve this by introducing delay sensors to monitor internal timing violations within a pipeline stage and variable clock skew buffers to adjust the timing of the pipeline stage based on the feedback from the delay sensors. Furthermore, we formulate the delay sensor insertion and variable clock skew configuration problem as a stochastic mixed-integer programming problem and propose a simulated-annealing based algorithm to solve it. A comparison between the designs with and without the self-adjusting enhancement reveals that, we are able to improve the average performance of a batch of chips by 9.5%.

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Section: Impact Of Process Variations On Timingmentioning

confidence: 99%

“…Majority of existing statistical yield optimization techniques are static [1][2][3][4]. However, we propose a dynamic technique that enables robustness towards process variations during run-time.…”

Section: Introductionmentioning

confidence: 99%

Automated design of self-adjusting pipelines

Long

Memik

2008

Proceedings of the 45th Annual Design Automation Conference

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“…Tschanz et al [7] propose adaptive body bias (ABB) and Narendra et al [11] propose forward body bias (FBB) to mitigate the impact of variation for several critical path structures, but neither of these studies consider system-level effects. Datta et al demonstrate that an unbalanced pipeline design can increase yield [5].…”

Section: Related Workmentioning

confidence: 99%

Microarchitecture Parameter Selection To Optimize System Performance Under Process Variation

Liang

Brooks

2006

2006 IEEE/ACM International Conference on Computer Aided Design

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Abstract-Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield of high-performance microprocessors in future process technology generations. This variability manifests itself by increasing the number and criticality of long delay paths. To quantify this impact, we use an architectural process variation model that is appropriate for the analysis of system performance in the earlystages of the design process. We propose a method of selecting microarchitectural parameters to mitigate the frequency impact due to process variability for distinct structures, while minimizing IPC (instructions-per-cycle) loss. We propose an optimization procedure to be used for system-level design decisions, and we find that joint architecture and statistical timing analysis can be more advantageous than pure circuit level optimization. Overall, the technique can improve the 90% yield frequency by about 14% with 3% IPC loss for a baseline machine with a 20FO4 logic depth per pipestage. This approach is sensitive to the selection of processor pipeline depth, and we demonstrate that machines with aggressive pipelines will experience greater challenges in coping with process variability.

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“…In the NT regime, the pipelined circuits should be designed not only energy-efficient, but also variability-tolerant. The authors in [11] developed a statistical methodology to enhance the yield of the pipelined circuits, considering the inter-die and intra-die variation. Recently, a two-phase latch-based design strategy is proposed for the synchronous pipelined circuits in the NT operation regime to derive the optimal ratio between the total width of sequential logic and that of combinational logic [10].…”

Section: Introductionmentioning

confidence: 99%

Variability-aware design of energy-delay optimal linear pipelines operating in the near-threshold regime and above

Xie

Wang

Pedram

2013

Proceedings of the 23rd ACM International Conference on Great Lakes Symposium on VLSI

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Soft-edge flip-flop based pipelines can improve the performance and energy efficiency of circuits operating in the super-threshold (supply voltage) regime by allowing opportunistic time borrowing. The application of this technique to nearthreshold regime of operation, however, faces a significant challenge due to large circuit parameter variations that result from manufacturing process imperfections and substrate temperature changes. This paper thus addresses the issue of variability-aware design of energy-delay optimal linear pipelines that are aimed at operating in both the near-threshold and super-threshold regimes. Precisely, this goal is achieved by deriving optimal delay line configuration included in the soft-edge flip-flop design for the near-threshold and the super-threshold operations. The key is to ensure that the same transistor sizes result in effective operation of the delay line (and hence appropriate setting of the transparency window size) in both regimes of operation under process induced variations. Experimental results demonstrate the efficacy of the proposed solution.

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Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies

Abstract: Abstract

Cited by 17 publications

References 9 publications

Automated design of self-adjusting pipelines

Automated design of self-adjusting pipelines

Microarchitecture Parameter Selection To Optimize System Performance Under Process Variation

Variability-aware design of energy-delay optimal linear pipelines operating in the near-threshold regime and above

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