Statistical process modelling for 32nm high-K/metal gate PMOS device

Maheran, A. H. Afifah; Faizah, Z. A. Noor; Menon, P. Susthitha; Ahmad, Ibrahim; Apte, P. R.; Kalaivani, T.; Salehuddin, F.

doi:10.1109/smelec.2014.6920839

Cited by 6 publications

(2 citation statements)

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“…After that, the metal gate was deposited to form the gate on top of the high-k material, La 2 O 3 . Figure 4 a shows the characteristic curve between the drain current ( I d ) and drain voltage ( V d ) at different gate voltages ( V g ) of 1.0 V, 1.1 V, 2.0 V, and 2.2 V, whereas Figure 4 b shows the plot of I d versus V g at V d = 0.1 V and 1.1 V, and V d = 0.05 V and 1.1 V, respectively, for the 14-nm and 22-nm devices [ 35 , 47 ]. V th was calculated by subtracting half of the applied drain bias from the overall slope of the I d -V g curve and determining the intercept with the x -axis.…”

Section: Resultsmentioning

confidence: 99%

“…A 14-nm La 2 O 3 -based PMOS was fabricated virtually using advanced-process simulation tools from SILVACO TCAD software, version 2020, by SILVACO International, Santa Clara, CA, USA. The design of the PMOS with high-k/metal gate (HKMG) technology was modelled based on previous research [ 35 , 36 ] and simulated using the ATHENA process simulator [ 37 ]. La 2 O 3 was identified to be the high-k oxide and tungsten as the metal gate for the fabricated PMOS [ 38 , 39 ].…”

Section: Methodsmentioning

confidence: 99%

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A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-Length

et al. 2021

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At the 90-nm node, the rate of transistor miniaturization slows down due to challenges in overcoming the increased leakage current (Ioff). The invention of high-k/metal gate technology at the 45-nm technology node was an enormous step forward in extending Moore’s Law. The need to satisfy performance requirements and to overcome the limitations of planar bulk transistor to scales below 22 nm led to the development of fully depleted silicon-on-insulator (FDSOI) and fin field-effect transistor (FinFET) technologies. The 28-nm wafer planar process is the most cost-effective, and scaling towards the sub-10 nm technology node involves the complex integration of new materials (Ge, III-V, graphene) and new device architectures. To date, planar transistors still command >50% of the transistor market and applications. This work aims to downscale a planar PMOS to a 14-nm gate length using La2O3 as the high-k dielectric material. The device was virtually fabricated and electrically characterized using SILVACO. Taguchi L9 and L27 were employed to study the process parameters’ variability and interaction effects to optimize the process parameters to achieve the required output. The results obtained from simulation using the SILVACO tool show good agreement with the nominal values of PMOS threshold voltage (Vth) of −0.289 V ± 12.7% and Ioff of less than 10−7 A/µm, as projected by the International Technology Roadmap for Semiconductors (ITRS). Careful control of SiO2 formation at the Si interface and rapid annealing processing are required to achieve La2O3 thermal stability at the target equivalent oxide thickness (EOT). The effects of process variations on Vth, Ion and Ioff were investigated. The improved voltage scaling resulting from the lower Vth value is associated with the increased Ioff due to the improved drain-induced barrier lowering as the gate length decreases. The performance of the 14-nm planar bulk PMOS is comparable to the performance of the FDSOI and FinFET technologies at the same gate length. The comparisons made with ITRS, the International Roadmap for Devices and Systems (IRDS), and the simulated and experimental data show good agreement and thus prove the validity of the developed model for PMOSs. Based on the results demonstrated, planar PMOSs could be a feasible alternative to FDSOI and FinFET in balancing the trade-off between performance and cost in the 14-nm process.

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Section: Resultsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%