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The evolution of MOSFET technology has been governed solely by device scaling, delivered an ever-increasing transistor density through Moore's Law. In this paper, the design, fabrication and characterization of 32nm HfO 2 /TiSi 2 PMOS device is presented; replacing the conventional SiO 2 dielectric and Poly-Silicon. The fabrication and simulation of PMOS transistor is performed via Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools namely ATHENA and ATLAS. Taguchi L9 Orthogonal method is then applied to this experiment for optimization of threshold voltage (V TH ) and leakage current (I OFF ). The simulation result shows that the optimal value of V TH and I OFF which are 0.1030075V and 3.4264075x10 -12 A/um respectively are well within ITRS prediction.

Abstract. This paper presents an inclusive study and analysis of graphene-based MOSFET device at 32nm gate length. The analysis was based on top-gated structure which utilized Hafnium Dioxide (HfO 2 ) dielectrics and metal gate. The same conventional process flows of a transistor were applied except the deposition of bilayer graphene as a channel. The analytical expression of the channel potential includes all relevant physics of bilayer graphene and by assuming that this device displays an ideal ohmic contact and functioned at a ballistic transport. Based on the designed transistor, the on-state current (I ON ) for both GNMOS and GPMOS shows a promising performance where the value is 982.857uA/um and 99.501uA/um respectively. The devices also possess a very small leakage current (I OFF ) of 0.289578nA/um for GNMOS and 0.130034nA/um for GPMOS as compared to the conventional SiO 2/ Poly-Si and high-k metal gate transistors. However, the devices suffer an inappropriate subthreshold swing (SS) and high value of drain induced barrier lowering (DIBL).

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