Statistical SPICE analysis of a 0.18 μm CMOS digital/analog technology during process development

Abstract

This paper gives details of a methodology to extract statistical SPICE models on a developing deep sub micron CMOS technology. The approach uses a TCAD framework which integrates process, device, parameter extraction, and statistics software. The TCAD tools are calibrated by physical and electrical measurements on transistor test structures with different channel lengths. Once calibrated, a Monte Carlo experiment is run on all process control input parameters with realistic variations and the results then compared to in-line and E-test distributions. When satisfied that the variance in TCAD and measured distributions match, the framework can be used to extract BSIM3v3.2 parameters to generate statistical models. Multivariate statistics is used to determine the key process parameters which need to be controlled in-line to minimize device variation. This methodology is demonstrated using Chartered Semiconductor Manufacturing Ltd's 0.18pm CMOS core logic technology. I. MOTIVATIONThe main objective of this work is to use Technology CAD (TCAD) to generate statistical SPICE models [ l ] for a developing deep sub micron CMOS technology. The aim is to use the same extraction strategy and tools for TCAD data as would be used for measurement data. Another goal from the statistical analysis is to identify key in-line process parameters which need to be monitored to minimise device variation. The ability to produce early statistical models by this method has the potential to help process optimisation and improve product yield. A calibrated TCAD framework can also be used to predict next generation SPICE models.NMOS device which has a drawn gate length of 0 . 1 8~m and a physical thin gate oxide thickness of 30A. TCAD CALIBRATIONTCAD is a key activity for the development and understanding of advanced CMOS technology. The main goal of characterizing a CMOS process using TCAD is to develop two decks (NMOS and PMOS) which model the effects on I-V curves for different channel lengths. Therefore, it is critical to model the non-uniform vertical and lateral channel profiles for different device types which need to be calibrated for each individual technology in order to model short channel effects on transistor threshold voltage. To calibrate process simulations in-line measurements from development silicon and SIMS measurements are used to match layer thickness' and doping profiles. Device simulations were calibrated using the first revision of transistor measurement characteristics from carefully designed modelling test structures (see figure 2), suitable for SPICE extraction, and initial E-test data.

Analysis of Process-Geometry Modulations through 3D TCAD

“…The use of TCAD to analyze and quantify process variations is well established in the industry. The common approach is to use twodimensional simulations to avoid the problems of complexity, cost, and accuracy that arise with three-dimensional simulations [1,2] . However, modern VLSI circuits use transistors that have not only a short channel, but are also narrow.…”