This paper gives details of a methodology to extract statistical SPICE models on a developing deep sub micron CMOS technology. The approach uses a TCAD framework which integrates process, device, parameter extraction, and statistics software. The TCAD tools are calibrated by physical and electrical measurements on transistor test structures with different channel lengths. Once calibrated, a Monte Carlo experiment is run on all process control input parameters with realistic variations and the results then compared to in-line and E-test distributions. When satisfied that the variance in TCAD and measured distributions match, the framework can be used to extract BSIM3v3.2 parameters to generate statistical models. Multivariate statistics is used to determine the key process parameters which need to be controlled in-line to minimize device variation. This methodology is demonstrated using Chartered Semiconductor Manufacturing Ltd's 0.18pm CMOS core logic technology. I. MOTIVATIONThe main objective of this work is to use Technology CAD (TCAD) to generate statistical SPICE models [ l ] for a developing deep sub micron CMOS technology. The aim is to use the same extraction strategy and tools for TCAD data as would be used for measurement data. Another goal from the statistical analysis is to identify key in-line process parameters which need to be monitored to minimise device variation. The ability to produce early statistical models by this method has the potential to help process optimisation and improve product yield. A calibrated TCAD framework can also be used to predict next generation SPICE models.NMOS device which has a drawn gate length of 0 . 1 8~m and a physical thin gate oxide thickness of 30A. TCAD CALIBRATIONTCAD is a key activity for the development and understanding of advanced CMOS technology. The main goal of characterizing a CMOS process using TCAD is to develop two decks (NMOS and PMOS) which model the effects on I-V curves for different channel lengths. Therefore, it is critical to model the non-uniform vertical and lateral channel profiles for different device types which need to be calibrated for each individual technology in order to model short channel effects on transistor threshold voltage. To calibrate process simulations in-line measurements from development silicon and SIMS measurements are used to match layer thickness' and doping profiles. Device simulations were calibrated using the first revision of transistor measurement characteristics from carefully designed modelling test structures (see figure 2), suitable for SPICE extraction, and initial E-test data.

This papcr prescnls a methodology for predicting the cffect of' proccss input pnramcter viiriation on SPICE parilmcters curly in the dcvclqmcnt of ii new process. This is iichievcd by using TCAD generated measurcmeiit data calibrated from tcst structure measurcment &in gathcred froni an initial process. This methodology enablcs the Sitme cxtrnction strategy to be petf(irmed on TCAD atid physical mcnsurcment data tliInughout the dcvelopment of n semiconductor process ensuring data integrity. This iissists both the proccss ititegration cnginecr and the dcsign engineer in the opriinisation uf a proccss.haw been reported on how to gcnccnre models at this slage 1:1-3]. This papcr takes a different approach by using test structurcs to characterise the base process. This information is then uscd to calibrate TCAD simulators. The outputs from the simulators are then uscd to prctiict clcctricnl proccsn distributions, and consequently SPICE pormnieter distributions, cnabling this information to be made avnilnblc to designers in A t i d y mariner. Tfic extrnctian strategy is portable for use on both TCAD and physical measurcnient data. Process dcveloprirent Yroceus frorozeiiProilrr crion b'igure I. Normal SPICE model revision relaled to process developmcnt.ICMTS 00-I87

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Technology CAD (TCAD) is a commonly used tool in process development and analysis. The task of creating the process in the required format for the TCAD deck is non-trivial and often prone to error due to the detailed nature of the furnace processing. Ensuring that the simulation deck is matched to the actual furnace process is also a key area. There is a difference between what is programmed into the furnace and what the wafers actually see. This work presents a method of automatic download of the actual furnace parameters to a format directly readable by the process simulator SUPREM, and examines the consequences of the furnace variability inherent in batch processing. The three furnace zones can be seen to interact and produce best-worst case simulations to aid in the prediction of manufacturability.

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