Statistical static timing analysis: how simple can we get?

Amin, C.S.; Menezes, N.; Killpack, K.; Dartu, F.; Choudhury, U.; Hakim, N.; Ismail, Y.I.

doi:10.1109/dac.2005.193892

Cited by 49 publications

(54 citation statements)

References 8 publications

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“…1 We now present the notion of flow equivalence [17], which is related to that of the synchronous behavior in [24], in terms of the projection of traces onto the latches of the circuit. The following theorem is the main theoretical result of this paper.…”

Section: ) Ifmentioning

confidence: 99%

“…In the case of delay and power, these uncertainties add up to huge margins that must be taken in order to ensure that a sufficiently large number of manufactured chips work correctly, i.e., within specifications. Statistical static timing analysis (SSTA, see, e.g., [1] and [26]) partially deals with the problem, by separating uncorrelated variations, whose effect is reduced because they quickly average out, and correlated variations, which must still be taken care of by margins.…”

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confidence: 99%

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Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications

Cortadella

Kondratyev

Lavagno

et al. 2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

147

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Abstract-Asynchronous implementation techniques, which measure logic delays at runtime and activate registers accordingly, are inherently more robust than their synchronous counterparts, which estimate worst case delays at design time and constrain the clock cycle accordingly. Desynchronization is a new paradigm to automate the design of asynchronous circuits from synchronous specifications, thus, permitting widespread adoption of asynchronicity without requiring special design skills or tools. In this paper, different protocols for desynchronization are first studied, and their correctness is formally proven using techniques originally developed for distributed deployment of synchronous language specifications. A taxonomy of existing protocols for asynchronous latch controllers, covering, in particular, the four-phase handshake protocols devised in the literature for micropipelines, is also provided. A new controller that exhibits provably maximal concurrency is then proposed, and the performance of desynchronized circuits is analyzed with respect to the original synchronous optimized implementation. Finally, this paper proves the feasibility and effectiveness of the proposed approach by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architecture.

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Section: ) Ifmentioning

confidence: 99%

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confidence: 99%

Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications

Cortadella

Kondratyev

Lavagno

et al. 2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

147

View full text Add to dashboard Cite

show abstract

“…Predicting the impact of manufacturing variation on circuit and architecture designs has become a challenging and increasingly important task for several reasons [1], [9]. The fabrication process introduces prominent variations to the threshold voltage, V th , and the effective gate length, L eff of transistors [1], [10], [11].…”

Section: Introductionmentioning

confidence: 99%

Efficient parameter variation sampling for architecture simulations

Lü

Joseph

Trajcevski

et al. 2011

2011 Design, Automation &Amp; Test in Europe

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Abstract-This paper addresses the problem of efficient and effective parameter variation modeling and sampling in computer architecture simulations. While there has been substantial progress in accelerating simulation time for circuit designs subject to manufacturing variations, these approaches are not generally suitable for architectural studies. Toward this we investigated two complementary avenues: (1) adapting low-discrepancy sampling methods for use in Monte Carlo architectural simulations. We apply techniques previously developed for gate-level circuit models to higher level component models and in so doing drastically reduce the number of samples needed for detailed simulation; (2) applying multi-resolution analysis to appropriately decompose geometric regions of a chip, and achieve more effective description of parameter variations without increasing computational complexity. Our experimental results demonstrate that the combined techniques can reduce the number of Monte Carlo trials by a factor of 3.3, maintaining the same accuracy while significantly reducing the overall simulation run-time.

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“…There are two approaches to static timing analysis: path-based [9][10][11][12][13][14] and block- -20]. The path-based approach can be regarded as a depth-first search, and it employs a given a set of critical paths.…”

Section: A Timing Analysismentioning

confidence: 99%

Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits

Kim

Walker

2006

Seventh International Workshop on Microprocessor Test and Verification (MTV'06)

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Chair of Advisory Committee: Dr. Duncan Moore Henry Walker As semiconductor technology is scaled and voltage level is reduced, the impact of the variation in power supply has become very significant in predicting the realistic worst-case delays in integrated circuits. The analysis of power supply noise is inevitable because high correlations exist between supply voltage and delay. Supply noise analysis has often used a vector-based timing analysis approach. Finding a set of test vectors in vector-based approaches, however, is very expensive, particularly during the design phase, and becomes intractable for larger circuits in DSM technology.In this work, two novel vectorless approaches are described such that increases in circuit delay, because of power supply noise, can be efficiently, quickly estimated.Experimental results on ISCAS89 circuits reveal the accuracy and efficiency of my approaches: in s38417 benchmark circuits, errors on circuit delay distributions are less than 2%, and both of my approaches are 67 times faster than the traditional vector-based approach. Also, the results show the importance of considering care-bits, which sensitize the longest paths during the power supply noise analysis.

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Statistical static timing analysis: how simple can we get?

Cited by 49 publications

References 8 publications

Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications

Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications

Efficient parameter variation sampling for architecture simulations

Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits

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