Statistical time borrowing for pulsed-latch circuit designs

Paik,; A, Yu; Shin, Jae Hoon

doi:10.1109/aspdac.2010.5419801

Cited by 13 publications

(5 citation statements)

References 5 publications

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“…The paths that constrain the design the most are those between pairs of same polarity FFs, because paths from PETF to NETF allow time borrowing and paths from NETF to PETF cannot be generated by Algorithm 2. This is why in (14) we consider the maximum between the two FF types, rather than the sum.…”

Section: B Area Comparisonmentioning

confidence: 99%

Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops

et al. 2023

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Flip-flops are the most used sequential elements in synchronous circuits, but designs based on latches can operate at higher frequencies and occupy less area. Techniques to increase the maximum operating frequency of flip-flop based designs, such as time-borrowing, rely on tight hold constraints that are difficult to satisfy using traditional back-end optimization techniques. We propose Mix & Latch, a methodology to increase the operating frequency of synchronous digital circuits using a single clock tree and a mixed distribution of positive-and negative-edge-triggered flops, and positive-and negative-levelsensitive latches. An efficient mathematical model is proposed to optimize the type and location of the sequential elements of the circuit. We ensure that the initial registers are not moved from their initial location, although they may change type, thus allowing the use of equivalence checking and static timing analysis to verify formally the correctness of the transformation. The technique is validated using a 28 nm CMOS FDSOI technology, obtaining 1.33 X post-layout average operating frequency improvement on a broad set of benchmarks over a standard commercial design flow. Additionally, the circuit area was also reduced by more than 1.19 X on average for the same benchmarks, although the overall area reduction is not a goal of the optimization algorithm. To the best of our knowledge, this is the first work that proposes combining mixed-polarity flip-flops and latches to improve the circuit performance.

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Section: B Area Comparisonmentioning

confidence: 99%

Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops

et al. 2023

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“…As an intermediate between latch and flip-flop based designs, pulsed-latch schemes have also been proposed [7,8]. These rely on an edge-triggered pulse generator to provide a short transparency window to all latches.…”

Section: Introductionmentioning

confidence: 99%

Saving Power by Converting Flip-Flop to 3-Phase Latch-Based Designs

Cheng

et al. 2020

2020 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Latch-based designs have many benefits over their flip-flop based counterparts but have limited use partially because most RTL specifications are flop-centric and automatic conversion of FF to latch-based designs is challenging. Conventional conversion algorithms target master-slave latchbased designs with two non-overlapping clocks. This paper presents a novel automated design flow that converts flipflop to 3-phase latch-based designs. The resulting circuits have the same performance as the master-slave based designs but require significantly less latches. Our experimental results demonstrate the potential for savings in the number of latches (21.3%), area (5.8%), and power (16.3%) on a variety of ISCAS, CEP, and CPU benchmark circuits, compared to the master-slave conversions. * This work was partially supported by NSF Grant #1619415 and DARPA Contract #HR001119C0070. P. A. Beerel also consults for Galois, Inc. in the area of asynchronous design. c denote the cycle time of the two-phase non-overlapping clocks and assuming E12 = E21 = Tc, Equation 1 implies e2 − e1 = T 2P c + e1 − e2 = Tc and thus, T 2P c = 2Tc. In other words, the frequency of the two-phase clocks must be half that of the original FF-based design.

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“…Recent research endeavors have been devoted to EDA solutions for pulsed-latch-based circuits [4][5][6][7][8][9][10][11][12][13]. Most of these works adopt the generic pulsed-latch structure illustrated in Figure 1(a) and flip-flop-like timing analysis.…”

Section: Introductionmentioning

confidence: 99%

“…Most of these works adopt the generic pulsed-latch structure illustrated in Figure 1(a) and flip-flop-like timing analysis. To minimize clock period, Lee et al in [5] [6] and Paik et al in [7] apply aggressive time borrowing techniques, e.g., clock skew scheduling, pulse width allocation, and retiming. These skews, retimed values and widths are derived based on a logic synthesized netlist instead of placement.…”

Section: Introductionmentioning

confidence: 99%

“…Under flip-flop-like timing analysis, prior works [5][6][7] use aggressive time borrowing techniques; however, various pulse widths, clock skew scheduling, and retiming may induce some difficulties on timing closure and functional verification. In fact, we can utilize only the intrinsic time borrowing 2 of latches to provide flexibility to relocate pulsed-latches as well as tolerate timing violations [3].…”

Section: Introductionmentioning

confidence: 99%

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Novel pulsed-latch replacement based on time borrowing and spiral clustering

Chang

Jiang

Yang

et al. 2012

Proceedings of the 2012 ACM International Symposium on International Symposium on Physical Design

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Flip-flops are the most common form of sequencing elements; however, they have a significantly higher sequencing overhead than latches in terms of delay, power, and area. Hence, pulsedlatches are promising to reduce power for high performance circuits. In this paper, we propose a novel pulsed-latch replacement approach to save power and satisfy timing constraints. We fully utilize the intrinsic time borrowing property of pulsed-latches and develop a spiral clustering method with clock gating consideration. In addition, spiral clustering works well for both rectangular and rectilinear shaped layouts; the latter are popular in modern IC design. Experimental results show that our approach can generate very power efficient results.

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Statistical time borrowing for pulsed-latch circuit designs

Cited by 13 publications

References 5 publications

Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops

Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops

Saving Power by Converting Flip-Flop to 3-Phase Latch-Based Designs

Novel pulsed-latch replacement based on time borrowing and spiral clustering

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