Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation

Enami, Takashi; Ninomiya, S.; Shinkai, Ken-ichi; Abe, Shinya; Hashimoto, Masanori

doi:10.1587/transfun.e93.a.2399

Cited by 3 publications

(6 citation statements)

References 14 publications

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“…On the other hand, the block-based analysis, which does not suffer from the number of paths, can cope with common paths by increasing the number of random variables [40]. Let us analyze Fig.…”

Section: Common Path Pessimismmentioning

confidence: 99%

From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era

Bing

Hashimoto

Schlichtmann

2018

IPSJ Transactions on System LSI Design Methodology

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In advanced technology nodes, transistors and interconnects with shrinking physical dimensions suffer large process variations during manufacturing and are prone to reliability issues. These underlying changes require an overhaul of the design methodologies for digital circuits. In this paper, we provide an overview of techniques introduced recently to analyze the effect of uncertainty in manufacturing and reliability issues of devices due to the diminishing feature size. These techniques range from variation/aging modeling to circuit-level analysis. In addition, active techniques to counter these effects, such as clock skew tuning and voltage tuning are also covered in this paper.

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Section: Common Path Pessimismmentioning

confidence: 99%

From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era

Bing

Hashimoto

Schlichtmann

2018

IPSJ Transactions on System LSI Design Methodology

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“…When f n increases from f n1 to f n2 , the propagation time of this edge decreases from t 1 to t 2 and the supply voltage within this duration increases. This higher supply voltage introduces lower σ in the buffer delay, which causes lower σ J (1,2) and σ S (1,2) according to (19) and (24). Proposition 6: The mean setup skitter increases significantly with the frequency of power supply noise, while both σ J 1,2 and σ S 1,2 decrease with this frequency.…”

Section: Effect Of F N On Skittermentioning

confidence: 99%

“…For 2-D ICs, a statistical timing analysis method considering process variations and power supply noise is proposed in [19], where full-chip simulations are required to obtain the distribution of power supply noise. Moreover, the effect of these variations on clock distribution networks is not adequately explored.…”

mentioning

confidence: 99%

Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise

Pavlidis

Tang

et al. 2013

IEEE Trans. VLSI Syst.

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“…The actual clock period for data transfer is determined by both clock skew and jitter. A statistical timing analysis method considering clock jitter and skew is proposed in [14], where the actual distribution of power supply noise is required. The contribution of skew and jitter on clock distribution networks, however, is not explored.…”

Section: Introductionmentioning

confidence: 99%

“…Although clock skew and jitter must be cohesively treated as discussed in [14]- [16], the combined effect of process variations and power supply noise on clock distribution networks has not been thoroughly explored. This effect is investigated in terms of skitter in this paper.…”

Section: Introductionmentioning

confidence: 99%

The combined effect of process variations and power supply noise on clock skew and jitter

Pavlidis

Burleson

et al. 2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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Abstract-In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock skew and jitter is investigated in this paper. A statistical model of skitter, which consists of skew and jitter, is proposed. Clock paths with different buffer insertion strategies are compared in terms of skew and jitter. The tradeoffs among the constraints on clock jitter, skew, slew rate, and power are discussed. For strict timing constraints, severe power overhead (≥ 110%) has to be added to obtain a low improvement in the worst case skitter and slew rate (≤ 13%). The effect of widelyused techniques, such as recombinant trees and dynamic voltage scaling, on decreasing skitter is also investigated.

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Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation

Cited by 3 publications

References 14 publications

From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era

From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era

Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise

The combined effect of process variations and power supply noise on clock skew and jitter

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